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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-17 21:03:19 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-17 21:03:19 +0000 |
| commit | dd5bc1f89399894ea31f61c2cd28f6390e1b7e50 (patch) | |
| tree | f9dca472c25b9edab55b58bf1ecb0717cf0e7179 /src | |
| parent | a13764b5d0619648b67bdc5435f69ca903b18736 (diff) | |
| download | openocd_libswd-dd5bc1f89399894ea31f61c2cd28f6390e1b7e50.tar.gz openocd_libswd-dd5bc1f89399894ea31f61c2cd28f6390e1b7e50.tar.bz2 openocd_libswd-dd5bc1f89399894ea31f61c2cd28f6390e1b7e50.tar.xz openocd_libswd-dd5bc1f89399894ea31f61c2cd28f6390e1b7e50.zip | |
Edwin Olsen: improves breakpoint handling on cortex-m3 parts. Specifically, this patch allows expressions to be evaluated in GDB that contain function calls.
git-svn-id: svn://svn.berlios.de/openocd/trunk@589 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_m3.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index b330fee3..fb303a8b 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -749,7 +749,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("breakpoint already set"); return ERROR_OK; } - + if (cortex_m3->auto_bp_type) { breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; @@ -831,10 +831,16 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - + if (cortex_m3->auto_bp_type) { breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + if (breakpoint->length != 2) { + // XXX Hack: Replace all breakpoints with length != 2 with + // a hardware breakpoint. + breakpoint->type = BKPT_HARD; + breakpoint->length = 2; + } } if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) @@ -1105,6 +1111,14 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + // If the LR register is being modified, make sure it will put us + // in "thumb" mode, or an INVSTATE exception will occur. This is a + // hack to deal with the fact that gdb will sometimes "forge" + // return addresses, and doesn't set the LSB correctly (i.e., when + // printing expressions containing function calls, it sets LR=0.) + if (num==14) + value |= 0x01; + if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) { retval = ahbap_write_coreregister_u32(swjdp, value, num); @@ -1449,3 +1463,4 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx) return retval; } + |