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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:20:25 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:20:25 +0000 |
| commit | f36d0083def304410418a174e140469a771a44a2 (patch) | |
| tree | 2282657d5ce632db8a700e3a4eae773d61cb2065 /src | |
| parent | 56b346447bb9799640ef328d4d867168be813119 (diff) | |
| download | openocd_libswd-f36d0083def304410418a174e140469a771a44a2.tar.gz openocd_libswd-f36d0083def304410418a174e140469a771a44a2.tar.bz2 openocd_libswd-f36d0083def304410418a174e140469a771a44a2.tar.xz openocd_libswd-f36d0083def304410418a174e140469a771a44a2.zip | |
Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_a8.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index dcf246fa..fd807232 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -259,14 +259,13 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; + uint32_t dscr; /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - if (reg > 16) return retval; @@ -286,10 +285,16 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); } - /* Read DCCTX */ + /* Read DTRRTX */ + do + { + retval = mem_ap_read_atomic_u32(swjdp, + OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + } + while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */ + retval = mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); -// retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); return retval; } |