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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-21 08:58:49 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-21 08:58:49 +0000 |
| commit | 0a7158140a2fb8a6bcd926c4ca2fc1385c515c80 (patch) | |
| tree | 79d16490ed85d9ec95114c031595bcf54d4747a6 /tcl/board/atmel_at91sam9260-ek.cfg | |
| parent | 8b73ec8d644920bfbdd1ca2d9e64a98207205e2e (diff) | |
| download | openocd_libswd-0a7158140a2fb8a6bcd926c4ca2fc1385c515c80.tar.gz openocd_libswd-0a7158140a2fb8a6bcd926c4ca2fc1385c515c80.tar.bz2 openocd_libswd-0a7158140a2fb8a6bcd926c4ca2fc1385c515c80.tar.xz openocd_libswd-0a7158140a2fb8a6bcd926c4ca2fc1385c515c80.zip | |
Pieter Conradie <Pieter.Conradie@psitek.com> Scripts for Atmel AT91SAM7S256 and AT91SAM9260
git-svn-id: svn://svn.berlios.de/openocd/trunk@2602 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board/atmel_at91sam9260-ek.cfg')
| -rw-r--r-- | tcl/board/atmel_at91sam9260-ek.cfg | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg new file mode 100644 index 00000000..6ff8fddb --- /dev/null +++ b/tcl/board/atmel_at91sam9260-ek.cfg @@ -0,0 +1,81 @@ +################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+# OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+ # At reset CPU runs at 32.768 kHz.
+ # JTAG Frequency must be 6 times slower if RCLK is not supported.
+ jtag_rclk 5
+ halt
+ # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+ arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
+ sleep 20 # wait 20 ms
+ mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
+ sleep 10 # wait 10 ms
+ mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+ sleep 20 # wait 20 ms
+ mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
+ sleep 10 # wait 10 ms
+ mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+ sleep 10 # wait 10 ms
+
+ # Increase JTAG Speed to 6 MHz if RCLK is not supported
+ jtag_rclk 6000
+
+ arm7_9 dcc_downloads enable # Enable faster DCC downloads
+
+ mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
+
+ mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+ mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+ mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0x20000000 0
+ mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0x20000000 0
+ mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
+}
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