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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:21:26 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:21:26 +0000 |
| commit | 56a04a3413a6427ef83dc18e3f7c7c13fd217113 (patch) | |
| tree | 3fc33bae7ef2da9d2dc6321b3b79947494c99411 /tcl/target/at91sam3u1c.cfg | |
| parent | f36d0083def304410418a174e140469a771a44a2 (diff) | |
| download | openocd_libswd-56a04a3413a6427ef83dc18e3f7c7c13fd217113.tar.gz openocd_libswd-56a04a3413a6427ef83dc18e3f7c7c13fd217113.tar.bz2 openocd_libswd-56a04a3413a6427ef83dc18e3f7c7c13fd217113.tar.xz openocd_libswd-56a04a3413a6427ef83dc18e3f7c7c13fd217113.zip | |
Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/target/at91sam3u1c.cfg')
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