diff options
| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
| commit | 71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch) | |
| tree | 9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/target | |
| parent | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff) | |
| download | openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.gz openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.bz2 openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.xz openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.zip | |
Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/target')
55 files changed, 455 insertions, 455 deletions
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg index 7e62735d..f7c5ee43 100644 --- a/tcl/target/aduc702x.cfg +++ b/tcl/target/aduc702x.cfg @@ -2,22 +2,22 @@ ## -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME aduc702x } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # This config file was defaulting to big endian.. set _ENDIAN little } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { set _CPUTAPID 0x3f0f0f0f } @@ -26,7 +26,7 @@ jtag_nsrst_delay 200 jtag_ntrst_delay 200 # This is for the case that TRST/SRST is not wired on your JTAG adaptor. -# Don't really need them anyways. +# Don't really need them anyways. reset_config none ## JTAG scan chain diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 213048ae..47bab1e3 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -29,11 +29,11 @@ $TARGETNAME configure -event reset-init { mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass mww 0xb8050008 1 # set clock_switch bit sleep 1 # wait for lock - + # Setup DDR config and flash mapping mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0) mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8) - + mww 0xb8000010 8 # force precharge all banks mww 0xb8000010 1 # force EMRS update cycle mww 0xb800000c 0 # clr ext. mode register @@ -47,7 +47,7 @@ $TARGETNAME configure -event reset-init { mww 0xb8000020 0 mww 0xb8000024 0 mww 0xb8000028 0 -} +} # setup working area somewhere in RAM $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 diff --git a/tcl/target/at91eb40a.cfg b/tcl/target/at91eb40a.cfg index 44f9f8e0..064a3b56 100644 --- a/tcl/target/at91eb40a.cfg +++ b/tcl/target/at91eb40a.cfg @@ -1,14 +1,14 @@ #Script for AT91EB40a -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at91eb40a } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -28,7 +28,7 @@ if { [info exists CPUTAPID ] } { #SRST reset, which means that the CPU will run a number #of cycles before it can be halted(as much as milliseconds). reset_config srst_only srst_pulls_trst - + #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID @@ -53,9 +53,9 @@ $_TARGETNAME configure -event reset-init { # Reset script for AT91EB40a reg cpsr 0x000000D3 mww 0xFFE00020 0x1 - mww 0xFFE00024 0x00000000 - mww 0xFFE00000 0x01002539 - mww 0xFFFFF124 0xFFFFFFFF + mww 0xFFE00024 0x00000000 + mww 0xFFE00000 0x01002539 + mww 0xFFFFF124 0xFFFFFFFF mww 0xffff0010 0x100 mww 0xffff0034 0x100 } diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg index 47542f6a..fe755b4d 100644 --- a/tcl/target/at91r40008.cfg +++ b/tcl/target/at91r40008.cfg @@ -1,14 +1,14 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at9r40008 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg index 0e672ff3..e20db520 100644 --- a/tcl/target/at91rm9200.cfg +++ b/tcl/target/at91rm9200.cfg @@ -3,15 +3,15 @@ reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at91rm9200 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -39,7 +39,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP # Create the GDB Target. set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME # AT91RM9200 has a 16K block of sram @ 0x0020.0000 $_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 \ diff --git a/tcl/target/at91sam3uXX.cfg b/tcl/target/at91sam3uXX.cfg index cfcc4a4f..26bb2a03 100644 --- a/tcl/target/at91sam3uXX.cfg +++ b/tcl/target/at91sam3uXX.cfg @@ -7,15 +7,15 @@ # at91sam3u2c # at91sam3u1c -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME sam3 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg index 80186eca..5cde979d 100644 --- a/tcl/target/at91sam7sx.cfg +++ b/tcl/target/at91sam7sx.cfg @@ -1,15 +1,15 @@ #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at91sam7s } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -24,26 +24,26 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi -$_TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { soft_reset_halt # RSTC_CR : Reset peripherals mww 0xfffffd00 0xa5000004 # disable watchdog - mww 0xfffffd44 0x00008000 + mww 0xfffffd44 0x00008000 # enable user reset - mww 0xfffffd08 0xa5000001 + mww 0xfffffd08 0xa5000001 # CKGR_MOR : enable the main oscillator - mww 0xfffffc20 0x00000601 + mww 0xfffffc20 0x00000601 sleep 10 # CKGR_PLLR: 96.1097 MHz - mww 0xfffffc2c 0x00481c0e + mww 0xfffffc2c 0x00481c0e sleep 10 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz - mww 0xfffffc30 0x00000007 + mww 0xfffffc30 0x00000007 sleep 10 # MC_FMR: flash mode (FWS=1,FMCN=73) - mww 0xffffff60 0x00490100 - sleep 100 + mww 0xffffff60 0x00490100 + sleep 100 } $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 diff --git a/tcl/target/at91sam9260.cfg b/tcl/target/at91sam9260.cfg index 6fc71a31..a6eaa76e 100644 --- a/tcl/target/at91sam9260.cfg +++ b/tcl/target/at91sam9260.cfg @@ -2,15 +2,15 @@ # Target: Atmel AT91SAM9260 ###################################### -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at91sam9260 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 11173604..2548962c 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -8,15 +8,15 @@ jtag_khz 4 # Target: Atmel AT91SAM9260 ###################################### -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME at91sam9260 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -59,7 +59,7 @@ flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME proc at91sam_init { } { - + # at reset chip runs at 32khz jtag_khz 8 halt diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg index e5b8600b..a0a28d80 100644 --- a/tcl/target/c100.cfg +++ b/tcl/target/c100.cfg @@ -5,15 +5,15 @@ # assume no PLL lock, start slowly jtag_khz 100 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME c100 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index f020f96e..b25dfd79 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -3,7 +3,7 @@ # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] proc config {label} { - return [dict get [configC100] $label ] + return [dict get [configC100] $label ] } # show the value for the param. with label @@ -15,7 +15,7 @@ proc showconfig {label} { # when there are more then one board config # use soft links to c100board-config.tcl # so that only the right board-config gets -# included (just like include/configs/board-configs.h +# included (just like include/configs/board-configs.h # in u-boot. proc configC100 {} { # xtal freq. 24MHz @@ -28,7 +28,7 @@ proc configC100 {} { # y = amba_clk * (w+1)*(x+1)*2/xtal_clk dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] - # Arm Clk 450MHz, must be a multiple of 25 MHz + # Arm Clk 450MHz, must be a multiple of 25 MHz dict set configC100 CFG_ARM_CLOCK 450000000 dict set configC100 w_arm 0 dict set configC100 x_arm 1 @@ -41,17 +41,17 @@ proc configC100 {} { proc setupNOR {} { puts "Setting up NOR: 16MB, 16-bit wide bus, CS0" # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() - set EX_CSEN_REG [regs EX_CSEN_REG ] - set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] - set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] - set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] - set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] - set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] + set EX_CSEN_REG [regs EX_CSEN_REG ] + set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] + set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] + set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] + set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] + set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] - set EX_MFSM_REG [regs EX_MFSM_REG ] - set EX_CSFSM_REG [regs EX_CSFSM_REG ] - set EX_WRFSM_REG [regs EX_WRFSM_REG ] - set EX_RDFSM_REG [regs EX_RDFSM_REG ] + set EX_MFSM_REG [regs EX_MFSM_REG ] + set EX_CSFSM_REG [regs EX_CSFSM_REG ] + set EX_WRFSM_REG [regs EX_WRFSM_REG ] + set EX_RDFSM_REG [regs EX_RDFSM_REG ] # enable Expansion Bus Clock + CS0 (NOR) mww $EX_CSEN_REG 0x3 @@ -62,7 +62,7 @@ proc setupNOR {} { # set timings to NOR mww $EX_CS0_TMG1_REG 0x03034006 mww $EX_CS0_TMG2_REG 0x04040002 - #mww $EX_CS0_TMG3_REG + #mww $EX_CS0_TMG3_REG # set EBUS clock 165/5=33MHz mww $EX_CLOCK_DIV_REG 0x5 # everthing else is OK with default @@ -72,7 +72,7 @@ proc bootNOR {} { set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] set BLOCK_RESET_REG [regs BLOCK_RESET_REG] set DDR_RST [regs DDR_RST] - + # put DDR controller in reset (so that it comes reset in u-boot) mmw $BLOCK_RESET_REG 0x0 $DDR_RST # setup CS0 controller for NOR @@ -93,8 +93,8 @@ proc setupGPIO {} { #GPIO17 reset for DECT module. #GPIO29 CS_n for NAND - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - set GPIO_OE_REG [regs GPIO_OE_REG] + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OE_REG [regs GPIO_OE_REG] # set GPIO29=GPIO17=1, GPIO5=0 mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] @@ -104,14 +104,14 @@ proc setupGPIO {} { proc highGPIO5 {} { puts "GPIO5 high" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=1 mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 } proc lowGPIO5 {} { puts "GPIO5 low" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=0 mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] } @@ -119,31 +119,31 @@ proc lowGPIO5 {} { proc boardID {id} { # so far built: # 4'b1111 - dict set boardID 15 name "EVT1" + dict set boardID 15 name "EVT1" dict set boardID 15 ddr2size 128M # dict set boardID 15 nandsize 1G # dict set boardID 15 norsize 16M # 4'b0000 - dict set boardID 0 name "EVT2" + dict set boardID 0 name "EVT2" dict set boardID 0 ddr2size 128M # 4'b0001 - dict set boardID 1 name "EVT3" + dict set boardID 1 name "EVT3" dict set boardID 1 ddr2size 256M # 4'b1110 dict set boardID 14 name "EVT3_old" dict set boardID 14 ddr2size 128M # 4'b0010 - dict set boardID 2 name "EVT4" + dict set boardID 2 name "EVT4" dict set boardID 2 ddr2size 256M return $boardID } # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() -# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors +# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors proc ooma_board_detect {} { set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - + # read the current value of the BOOTSRAP pins set tmp [mrw $GPIO_BOOTSTRAP_REG] puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] @@ -187,9 +187,9 @@ proc configureDDR2regs_128M {} { set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] - set DENALI_CTL_02_VAL 0x0100010000010100 + set DENALI_CTL_02_VAL 0x0100010000010100 set DENALI_CTL_11_VAL 0x433A42124A650A37 - # set some default values + # set some default values mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL @@ -218,7 +218,7 @@ proc configureDDR2regs_128M {} { # wait int_status[2] (DRAM init complete) puts -nonewline "Waiting for DDR2 controller to init..." set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + while { [expr $tmp & 0x040000] == 0 } { sleep 1 set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] } @@ -237,18 +237,18 @@ proc setupUART0 {} { set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] - set UART0_LCR [regs UART0_LCR] - set LCR_DLAB [regs LCR_DLAB] - set UART0_DLL [regs UART0_DLL] - set UART0_DLH [regs UART0_DLH] - set UART0_IIR [regs UART0_IIR] - set UART0_IER [regs UART0_IER] - set LCR_ONE_STOP [regs LCR_ONE_STOP] - set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] + set UART0_LCR [regs UART0_LCR] + set LCR_DLAB [regs LCR_DLAB] + set UART0_DLL [regs UART0_DLL] + set UART0_DLH [regs UART0_DLH] + set UART0_IIR [regs UART0_IIR] + set UART0_IER [regs UART0_IER] + set LCR_ONE_STOP [regs LCR_ONE_STOP] + set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] set FCR_XMITRES [regs FCR_XMITRES] - set FCR_RCVRRES [regs FCR_RCVRRES] - set FCR_FIFOEN [regs FCR_FIFOEN] - set IER_UUE [regs IER_UUE] + set FCR_RCVRRES [regs FCR_RCVRRES] + set FCR_FIFOEN [regs FCR_FIFOEN] + set IER_UUE [regs IER_UUE] # unlock writing to IOCTRL register mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL @@ -274,7 +274,7 @@ proc setupUART0 {} { proc putcUART0 {char} { - set UART0_LSR [regs UART0_LSR] + set UART0_LSR [regs UART0_LSR] set UART0_THR [regs UART0_THR] set LSR_TEMT [regs LSR_TEMT] @@ -311,7 +311,7 @@ proc trainDDR2 {} { proc flashUBOOT {} { # this will update uboot on NOR partition set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] - + # setup CS0 controller for NOR setupNOR # make sure we are accessing the lower part of NOR diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 5ed88f5e..b5e01646 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -61,17 +61,17 @@ proc mmw {reg setbits clearbits} { proc showNOR {} { puts "This is the current NOR setup" - set EX_CSEN_REG [regs EX_CSEN_REG ] - set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] - set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] - set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] - set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] - set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] + set EX_CSEN_REG [regs EX_CSEN_REG ] + set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] + set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] + set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] + set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] + set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] - set EX_MFSM_REG [regs EX_MFSM_REG ] - set EX_CSFSM_REG [regs EX_CSFSM_REG ] - set EX_WRFSM_REG [regs EX_WRFSM_REG ] - set EX_RDFSM_REG [regs EX_RDFSM_REG ] + set EX_MFSM_REG [regs EX_MFSM_REG ] + set EX_CSFSM_REG [regs EX_CSFSM_REG ] + set EX_WRFSM_REG [regs EX_WRFSM_REG ] + set EX_RDFSM_REG [regs EX_RDFSM_REG ] puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]] puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]] @@ -91,21 +91,21 @@ proc showNOR {} { proc showGPIO {} { puts "This is the current GPIO register setup" # GPIO outputs register - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # GPIO Output Enable register - set GPIO_OE_REG [regs GPIO_OE_REG] - set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG] - set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG] + set GPIO_OE_REG [regs GPIO_OE_REG] + set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG] + set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG] # GPIO input register - set GPIO_INPUT_REG [regs GPIO_INPUT_REG] - set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] - set MUX_CONF_REG [regs MUX_CONF_REG] - set SYSCONF_REG [regs SYSCONF_REG] - set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG] - set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - set GPIO_LOCK_REG [regs GPIO_LOCK_REG] - set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] - set GPIO_DEVID_REG [regs GPIO_DEVID_REG] + set GPIO_INPUT_REG [regs GPIO_INPUT_REG] + set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] + set MUX_CONF_REG [regs MUX_CONF_REG] + set SYSCONF_REG [regs SYSCONF_REG] + set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG] + set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] + set GPIO_LOCK_REG [regs GPIO_LOCK_REG] + set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] + set GPIO_DEVID_REG [regs GPIO_DEVID_REG] puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]] puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]] @@ -129,7 +129,7 @@ proc showAmbaClk {} { set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - + puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1 # see if the PLL is in bypass mode @@ -153,13 +153,13 @@ proc showAmbaClk {} { # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk()) # this clock is useb by all peripherals (DDR2, ethernet, ebus, etc) proc setupAmbaClk {} { - set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] + set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] set ARM_AHB_BYP [regs ARM_AHB_BYP] set PLL_DISABLE [regs PLL_DISABLE] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] set DIV_BYPASS [regs DIV_BYPASS] set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK] set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] @@ -204,7 +204,7 @@ proc showArmClk {} { set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL] set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - + puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1 # see if the PLL is in bypass mode @@ -232,8 +232,8 @@ proc setupArmClk {} { set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] set ARM_AHB_BYP [regs ARM_AHB_BYP] set PLL_DISABLE [regs PLL_DISABLE] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] set DIV_BYPASS [regs DIV_BYPASS] set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK] set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] @@ -283,12 +283,12 @@ proc setupPLL {} { # converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init() proc setupDDR2 {} { puts "Configuring DDR2" - + set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR] - set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR] + set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR] set MEMORY_CR [regs MEMORY_CR] - set BLOCK_RESET_REG [regs BLOCK_RESET_REG] - set DDR_RST [regs DDR_RST] + set BLOCK_RESET_REG [regs BLOCK_RESET_REG] + set DDR_RST [regs DDR_RST] # put DDR controller in reset (so that it is reset and correctly configured) # this is only necessary if DDR was previously confiured @@ -334,7 +334,7 @@ proc setupDDR2 {} { proc showDDR2 {} { - + set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] @@ -399,22 +399,22 @@ proc showDDR2 {} { puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)] set tmp [mr64bit $DENALI_CTL_20_DATA] puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)] - + } proc initC100 {} { - # this follows u-boot/cpu/arm1136/start.S - set GPIO_LOCK_REG [regs GPIO_LOCK_REG] - set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] - set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] + # this follows u-boot/cpu/arm1136/start.S + set GPIO_LOCK_REG [regs GPIO_LOCK_REG] + set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] + set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR] - set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG] + set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG] set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR] - set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG] + set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG] set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN] - set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN] - set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN] + set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN] + set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN] set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN] set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN] set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN] @@ -428,7 +428,7 @@ proc initC100 {} { # set ARM into supervisor mode (SVC32) # disable IRQ, FIQ # Do I need this in JTAG mode? - # it really should be done as 'and ~0x1f | 0xd3 but + # it really should be done as 'and ~0x1f | 0xd3 but # openocd does not support this yet reg cpsr 0xd3 # /* @@ -444,12 +444,12 @@ proc initC100 {} { # * disable MMU stuff and caches # */ # mrc p15, 0, r0, c1, c0, 0 - arm11 mrc c100.cpu 15 0 1 0 0 + arm11 mrc c100.cpu 15 0 1 0 0 # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) # orr r0, r0, #0x00000002 @ set bit 2 (A) Align # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - # orr r0, r0, #0x00400000 @ set bit 22 (U) + # orr r0, r0, #0x00400000 @ set bit 22 (U) # mcr p15, 0, r0, c1, c0, 0 arm11 mcr c100.cpu 15 0 1 0 0 0x401002 # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c @@ -464,10 +464,10 @@ proc initC100 {} { mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 # ARAM init - # // disable pipeline mode in ARAM + # // disable pipeline mode in ARAM # I don't think this is documented anywhere? mww $INTC_ARM1_CONTROL_REG 0x1 - # configure clocks + # configure clocks setupPLL # enable cache # ? (u-boot does nothing here) @@ -481,9 +481,9 @@ proc initC100 {} { # show current state of watchdog timer proc showWatchdog {} { set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] - set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] + set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] - + puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]] puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]] puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] @@ -495,7 +495,7 @@ proc showWatchdog {} { # watchdog reset effectively works as hw. reset proc reboot {} { set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] - set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] + set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] # allow the counter to count to high value before triggering @@ -508,10 +508,10 @@ proc reboot {} { mww $TIMER_WDT_CONTROL 0x1 # wait until the reset puts -nonewline "Wating for watchdog to trigger..." - #while {[mrw $TIMER_WDT_CONTROL] == 1} { - # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] - # sleep 1 - # + #while {[mrw $TIMER_WDT_CONTROL] == 1} { + # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] + # sleep 1 + # #} while {[c100.cpu curstate] != "running"} { sleep 1} puts "done." diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl index f59a92c7..56f07715 100644 --- a/tcl/target/c100regs.tcl +++ b/tcl/target/c100regs.tcl @@ -7,7 +7,7 @@ # For example: # set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG] proc regs {reg} { - return [dict get [regsC100] $reg ] + return [dict get [regsC100] $reg ] } proc showreg {reg} { @@ -19,13 +19,13 @@ proc regsC100 {} { #/* device memory base addresses */ #// device memory sizes #/* ARAM SIZE=64K */ -dict set regsC100 ARAM_SIZE 0x00010000 +dict set regsC100 ARAM_SIZE 0x00010000 dict set regsC100 ARAM_BASEADDR 0x0A000000 #/* Hardware Interface Units */ dict set regsC100 APB_BASEADDR 0x10000000 #/* APB_SIZE=16M address range */ -dict set regsC100 APB_SIZE 0x01000000 +dict set regsC100 APB_SIZE 0x01000000 dict set regsC100 EXP_CS0_BASEADDR 0x20000000 dict set regsC100 EXP_CS1_BASEADDR 0x24000000 @@ -212,7 +212,7 @@ dict set regsC100 EX_RDY_EDGE 0x00000800 # GPIO outputs register dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00] -# GPIO Output Enable register +# GPIO Output Enable register dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04] dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08] dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C] @@ -285,74 +285,74 @@ dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18] dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C] # /* default */ -dict set regsC100 LCR_CHAR_LEN_5 0x00 +dict set regsC100 LCR_CHAR_LEN_5 0x00 dict set regsC100 LCR_CHAR_LEN_6 0x01 dict set regsC100 LCR_CHAR_LEN_7 0x02 dict set regsC100 LCR_CHAR_LEN_8 0x03 #/* One stop bit! - default */ dict set regsC100 LCR_ONE_STOP 0x00 -#/* Two stop bit! */ -dict set regsC100 LCR_TWO_STOP 0x04 +#/* Two stop bit! */ +dict set regsC100 LCR_TWO_STOP 0x04 #/* Parity Enable */ -dict set regsC100 LCR_PEN 0x08 +dict set regsC100 LCR_PEN 0x08 dict set regsC100 LCR_PARITY_NONE 0x00 #/* Even Parity Select */ -dict set regsC100 LCR_EPS 0x10 +dict set regsC100 LCR_EPS 0x10 #/* Enable Parity Stuff */ -dict set regsC100 LCR_PS 0x20 +dict set regsC100 LCR_PS 0x20 #/* Start Break */ -dict set regsC100 LCR_SBRK 0x40 +dict set regsC100 LCR_SBRK 0x40 #/* Parity Stuff Bit */ -dict set regsC100 LCR_PSB 0x80 +dict set regsC100 LCR_PSB 0x80 #/* UART 16550 Divisor Latch Assess */ -dict set regsC100 LCR_DLAB 0x80 +dict set regsC100 LCR_DLAB 0x80 #/* FIFO Error Status */ -dict set regsC100 LSR_FIFOE [expr 1 << 7] +dict set regsC100 LSR_FIFOE [expr 1 << 7] #/* Transmitter Empty */ dict set regsC100 LSR_TEMT [expr 1 << 6] #/* Transmit Data Request */ -dict set regsC100 LSR_TDRQ [expr 1 << 5] +dict set regsC100 LSR_TDRQ [expr 1 << 5] #/* Break Interrupt */ -dict set regsC100 LSR_BI [expr 1 << 4] +dict set regsC100 LSR_BI [expr 1 << 4] #/* Framing Error */ -dict set regsC100 LSR_FE [expr 1 << 3] +dict set regsC100 LSR_FE [expr 1 << 3] #/* Parity Error */ -dict set regsC100 LSR_PE [expr 1 << 2] +dict set regsC100 LSR_PE [expr 1 << 2] #/* Overrun Error */ -dict set regsC100 LSR_OE [expr 1 << 1] +dict set regsC100 LSR_OE [expr 1 << 1] #/* Data Ready */ -dict set regsC100 LSR_DR [expr 1 << 0] +dict set regsC100 LSR_DR [expr 1 << 0] #/* DMA Requests Enable */ -dict set regsC100 IER_DMAE [expr 1 << 7] +dict set regsC100 IER_DMAE [expr 1 << 7] #/* UART Unit Enable */ -dict set regsC100 IER_UUE [expr 1 << 6] +dict set regsC100 IER_UUE [expr 1 << 6] #/* NRZ coding Enable */ -dict set regsC100 IER_NRZE [expr 1 << 5] +dict set regsC100 IER_NRZE [expr 1 << 5] #/* Receiver Time Out Interrupt Enable */ -dict set regsC100 IER_RTIOE [expr 1 << 4] +dict set regsC100 IER_RTIOE [expr 1 << 4] #/* Modem Interrupt Enable */ -dict set regsC100 IER_MIE [expr 1 << 3] +dict set regsC100 IER_MIE [expr 1 << 3] #/* Receiver Line Status Interrupt Enable */ -dict set regsC100 IER_RLSE [expr 1 << 2] +dict set regsC100 IER_RLSE [expr 1 << 2] #/* Transmit Data request Interrupt Enable */ -dict set regsC100 IER_TIE [expr 1 << 1] +dict set regsC100 IER_TIE [expr 1 << 1] #/* Receiver Data Available Interrupt Enable */ -dict set regsC100 IER_RAVIE [expr 1 << 0] +dict set regsC100 IER_RAVIE [expr 1 << 0] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES1 [expr 1 << 7] +dict set regsC100 IIR_FIFOES1 [expr 1 << 7] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES0 [expr 1 << 6] +dict set regsC100 IIR_FIFOES0 [expr 1 << 6] #/* Time Out Detected */ -dict set regsC100 IIR_TOD [expr 1 << 3] +dict set regsC100 IIR_TOD [expr 1 << 3] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID2 [expr 1 << 2] +dict set regsC100 IIR_IID2 [expr 1 << 2] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID1 [expr 1 << 1] +dict set regsC100 IIR_IID1 [expr 1 << 1] #/* Interrupt Pending (active low) */ -dict set regsC100 IIR_IP [expr 1 << 0] +dict set regsC100 IIR_IP [expr 1 << 0] #/* UART 16550 FIFO Control Register */ dict set regsC100 FCR_FIFOEN 0x01 @@ -362,14 +362,14 @@ dict set regsC100 FCR_XMITRES 0x04 #/* Interrupt Enable Register */ #// UART 16550 #// Enable Received Data Available Interrupt -dict set regsC100 IER_RXTH 0x01 +dict set regsC100 IER_RXTH 0x01 #// Enable Transmitter Empty Interrupt -dict set regsC100 IER_TXTH 0x02 +dict set regsC100 IER_TXTH 0x02 #//////////////////////////////////////////////////////////// -#// CLK + RESET block +#// CLK + RESET block #//////////////////////////////////////////////////////////// dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00] diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg index 18475ff5..237754ba 100644 --- a/tcl/target/cs351x.cfg +++ b/tcl/target/cs351x.cfg @@ -1,12 +1,12 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME cs351x } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg index 9eea39b5..f3fe7eb1 100644 --- a/tcl/target/epc9301.cfg +++ b/tcl/target/epc9301.cfg @@ -1,14 +1,14 @@ # Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME ep9301 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg index 25d1d133..b7077706 100644 --- a/tcl/target/feroceon.cfg +++ b/tcl/target/feroceon.cfg @@ -2,15 +2,15 @@ # Target: Marvell Feroceon CPU core ###################################### -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME feroceon } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/imx21.cfg b/tcl/target/imx21.cfg index 6644ce55..410bce8f 100644 --- a/tcl/target/imx21.cfg +++ b/tcl/target/imx21.cfg @@ -3,20 +3,20 @@ # Hmmm.... should srst_pulls_trst be used here like i.MX27??? reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME imx21 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } -# Note above there is 1 tap +# Note above there is 1 tap # The CPU tap if { [info exists CPUTAPID ] } { diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg index f12e8784..837ea614 100644 --- a/tcl/target/imx27.cfg +++ b/tcl/target/imx27.cfg @@ -6,20 +6,20 @@ # failing, etc. reset_config trst_and_srst srst_pulls_trst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME imx27 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } -# Note above there are 2 taps +# Note above there are 2 taps # The bs tap if { [info exists BSTAPID ] } { diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index fa7e2d21..ad99975b 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -3,15 +3,15 @@ reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME imx31 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -28,7 +28,7 @@ if { [info exists SDMATAPID ] } { } #======================================== -# The "system jtag controller" +# The "system jtag controller" # IMX31 reference manual, page 6-28 - figure 6-14 if { [info exists SJCTAPID ] } { set _SJCTAPID $SJCTAPID @@ -42,8 +42,8 @@ jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJ # See diagram: 6-14 # SIGNAL NAME: # SJC_MOD - controls multiplexer - disables ARM1136 -# SDMA_BYPASS - disables SDMA - -# +# SDMA_BYPASS - disables SDMA - +# # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID @@ -58,5 +58,5 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -proc power_restore {} { puts "Sensed power restore. No action." } +proc power_restore {} { puts "Sensed power restore. No action." } proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg index d7561657..446eef62 100644 --- a/tcl/target/imx35.cfg +++ b/tcl/target/imx35.cfg @@ -1,15 +1,15 @@ # imx35 config # -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME imx35 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -26,7 +26,7 @@ if { [info exists SDMATAPID ] } { } #======================================== -# The "system jtag controller" +# The "system jtag controller" # IMX31 reference manual, page 6-28 - figure 6-14 if { [info exists SJCTAPID ] } { set _SJCTAPID $SJCTAPID @@ -46,5 +46,5 @@ jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -proc power_restore {} { puts "Sensed power restore. No action." } +proc power_restore {} { puts "Sensed power restore. No action." } proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg index be7727db..8c153347 100644 --- a/tcl/target/is5114.cfg +++ b/tcl/target/is5114.cfg @@ -2,15 +2,15 @@ # AKA: Atmel AT76C114 - an ARM946 chip # ATMEL sold his product line to Insilica... -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME is5114 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a little endian set _ENDIAN little } @@ -29,7 +29,7 @@ reset_config trst_and_srst # Do not specify a tap id here... #OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe -jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 +jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 #OLD SYNTAX: jtag_device 4 0x1 0xf 0xe # This is the "arm946" chip. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf @@ -37,7 +37,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 -#arm946e-s and +#arm946e-s and set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index fbb227bb..6d2ecb70 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -1,15 +1,15 @@ #xscale ixp42x CPU -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME ixp42x } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN big } diff --git a/tcl/target/lm3s1968.cfg b/tcl/target/lm3s1968.cfg index 3f0cdfcf..e54bbfe5 100644 --- a/tcl/target/lm3s1968.cfg +++ b/tcl/target/lm3s1968.cfg @@ -1,8 +1,8 @@ # Script for TI/Luminary Stellaris LM3S1968 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lm3s1968 } diff --git a/tcl/target/lm3s3748.cfg b/tcl/target/lm3s3748.cfg index 3fdbd798..5317a6d9 100644 --- a/tcl/target/lm3s3748.cfg +++ b/tcl/target/lm3s3748.cfg @@ -1,8 +1,8 @@ # TI/Luminary Stellaris lm3s3748 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lm3s3748 } diff --git a/tcl/target/lm3s6965.cfg b/tcl/target/lm3s6965.cfg index c12b48d7..f0eb6b0d 100644 --- a/tcl/target/lm3s6965.cfg +++ b/tcl/target/lm3s6965.cfg @@ -1,8 +1,8 @@ # TI/Luminary Stellaris lm3s6965 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lm3s6965 } diff --git a/tcl/target/lm3s811.cfg b/tcl/target/lm3s811.cfg index f9e29832..82106961 100644 --- a/tcl/target/lm3s811.cfg +++ b/tcl/target/lm3s811.cfg @@ -1,8 +1,8 @@ # Script for TI/Luminary Stellaris LM3S811 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lm3s811 } diff --git a/tcl/target/lm3s9b9x.cfg b/tcl/target/lm3s9b9x.cfg index 56f492f6..e822bb28 100644 --- a/tcl/target/lm3s9b9x.cfg +++ b/tcl/target/lm3s9b9x.cfg @@ -5,9 +5,9 @@ # http://www.luminarymicro.com/products/lm3s9b92.htm # -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lm3s9b9x } diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg index b3a2262f..899ca237 100644 --- a/tcl/target/lpc2103.cfg +++ b/tcl/target/lpc2103.cfg @@ -1,6 +1,6 @@ # NXP LPC2103 ARM7TDMI-S with 32kB Flash and 8kB SRAM, clocked with 12MHz crystal -if { [info exists CHIPNAME] } { +if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc2103 @@ -15,7 +15,7 @@ if { [info exists ENDIAN] } { if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x4f1f0f0f + set _CPUTAPID 0x4f1f0f0f } # LPC2000 -> SRST causes TRST diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg index 428883d3..daaa8d56 100644 --- a/tcl/target/lpc2129.cfg +++ b/tcl/target/lpc2129.cfg @@ -1,15 +1,15 @@ #LPC-2129 CPU -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lpc2129 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg index fd939d99..e70947fe 100644 --- a/tcl/target/lpc2148.cfg +++ b/tcl/target/lpc2148.cfg @@ -1,9 +1,9 @@ -# Use RCLK. If RCLK is not available fall back to 500kHz. -# +# Use RCLK. If RCLK is not available fall back to 500kHz. +# # Depending on cabling you might be able to eek this up to 2000kHz. jtag_rclk 500 -if { [info exists CHIPNAME] } { +if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc2148 diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg index d20f0d30..399b11df 100644 --- a/tcl/target/lpc2294.cfg +++ b/tcl/target/lpc2294.cfg @@ -1,12 +1,12 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lpc2294 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/netx500.cfg b/tcl/target/netx500.cfg index 7dafdc0d..66f4a2eb 100644 --- a/tcl/target/netx500.cfg +++ b/tcl/target/netx500.cfg @@ -1,15 +1,15 @@ #Hilscher netX 500 CPU -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME netx500 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index 83f4ec1d..27e5b007 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -2,9 +2,9 @@ # http://focus.ti.com/docs/prod/folders/print/omap3530.html # Other OMAP3 chips remove DSP and/or the OpenGL support -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME omap3530 } diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg index 1a327929..6abbd3fa 100644 --- a/tcl/target/omap5912.cfg +++ b/tcl/target/omap5912.cfg @@ -1,15 +1,15 @@ # TI OMAP5912 dual core processor # http://focus.ti.com/docs/prod/folders/print/omap5912.html -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME omap5912 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN little } diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index 009a3cd1..daa54eb9 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -1,13 +1,13 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME pic32mx } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index 93d27bd3..1608d66c 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -1,15 +1,15 @@ # PXA255 chip ... originally from Intel, PXA line was sold to Marvell. # This chip is now at end-of-life. Final orders have been taken. -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME pxa255 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg index 6f209f89..81ecac7e 100644 --- a/tcl/target/pxa270.cfg +++ b/tcl/target/pxa270.cfg @@ -1,14 +1,14 @@ #Marvell/Intel PXA270 Script -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME pxa270 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt index ca23c64b..39f8d124 100644 --- a/tcl/target/readme.txt +++ b/tcl/target/readme.txt @@ -1,5 +1,5 @@ Prerequisites: -The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands +The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands do the same thing across all the targets. Rules to follow when writing scripts: @@ -8,20 +8,20 @@ Rules to follow when writing scripts: reset flash info <bank> and - reset + reset flash erase_address <start> <len> and reset init load - -In most cases this can be accomplished by specifying the default startup mode as reset_init (target command + +In most cases this can be accomplished by specifying the default startup mode as reset_init (target command in the configuration file). - -2. If the target is correctly configured, flash must be writable without any other helper commands. It is + +2. If the target is correctly configured, flash must be writable without any other helper commands. It is assumed that all write-protect mechanisms should be disabled. 3. The configuration scripts should be defined such as the binary that was written to flash verifies -(turn off remapping, checksums, etc...) +(turn off remapping, checksums, etc...) flash write_image [file] <parameters> verify_image [file] <parameters> diff --git a/tcl/target/sam7se512.cfg b/tcl/target/sam7se512.cfg index 98e952c3..4b1d85bf 100644 --- a/tcl/target/sam7se512.cfg +++ b/tcl/target/sam7se512.cfg @@ -1,17 +1,17 @@ -# ATMEL sam7se512 +# ATMEL sam7se512 # Example: the "Elektor Internet Radio" - EIR # http://www.ethernut.de/en/hardware/eir/index.html -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME sam7se512 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } diff --git a/tcl/target/sam7x256.cfg b/tcl/target/sam7x256.cfg index b659dd5f..12f30305 100644 --- a/tcl/target/sam7x256.cfg +++ b/tcl/target/sam7x256.cfg @@ -1,15 +1,15 @@ #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME sam7x256 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -24,22 +24,22 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi -$_TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { # disable watchdog - mww 0xfffffd44 0x00008000 + mww 0xfffffd44 0x00008000 # enable user reset - mww 0xfffffd08 0xa5000001 + mww 0xfffffd08 0xa5000001 # CKGR_MOR : enable the main oscillator - mww 0xfffffc20 0x00000601 + mww 0xfffffc20 0x00000601 sleep 10 # CKGR_PLLR: 96.1097 MHz - mww 0xfffffc2c 0x00481c0e + mww 0xfffffc2c 0x00481c0e sleep 10 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz - mww 0xfffffc30 0x00000007 + mww 0xfffffc30 0x00000007 sleep 10 # MC_FMR: flash mode (FWS=1,FMCN=60) - mww 0xffffff60 0x003c0100 + mww 0xffffff60 0x003c0100 sleep 100 } diff --git a/tcl/target/samsung_s3c2410.cfg b/tcl/target/samsung_s3c2410.cfg index 6dca7efd..e845eb59 100644 --- a/tcl/target/samsung_s3c2410.cfg +++ b/tcl/target/samsung_s3c2410.cfg @@ -1,21 +1,21 @@ # Found on the 'TinCanTools' Hammer board. -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c2410 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # This config file was defaulting to big endian.. set _ENDIAN little } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { set _CPUTAPID 0xffffffff } diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg index 4cfa4d82..f9263a52 100644 --- a/tcl/target/samsung_s3c2440.cfg +++ b/tcl/target/samsung_s3c2440.cfg @@ -3,15 +3,15 @@ # Processor : ARM920Tid(wb) rev 0 (v4l) # Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c2440 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN little } diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg index ec77291d..071b271a 100644 --- a/tcl/target/samsung_s3c2450.cfg +++ b/tcl/target/samsung_s3c2450.cfg @@ -4,9 +4,9 @@ # FIX!!! what to use here? -# +# # RCLK? -# +# # jtag_khz 0 # # Really low clock during reset? diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg index b594e329..f1cbff74 100644 --- a/tcl/target/samsung_s3c4510.cfg +++ b/tcl/target/samsung_s3c4510.cfg @@ -1,13 +1,13 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c4510 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -21,5 +21,5 @@ if { [info exists CPUTAPID ] } { jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg index fd9031be..594d3216 100644 --- a/tcl/target/samsung_s3c6410.cfg +++ b/tcl/target/samsung_s3c6410.cfg @@ -6,15 +6,15 @@ # [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places] # [and I do not believe it to be accurate, hence the 0xffffffff below] -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c6410 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN little } diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg index c04b8167..ed9feeea 100644 --- a/tcl/target/sharp_lh79532.cfg +++ b/tcl/target/sharp_lh79532.cfg @@ -1,14 +1,14 @@ reset_config srst_only srst_pulls_trst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME lh79532 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -21,6 +21,6 @@ if { [info exists CPUTAPID ] } { jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg index b2c63783..a37e7334 100644 --- a/tcl/target/stm32.cfg +++ b/tcl/target/stm32.cfg @@ -1,14 +1,14 @@ # script for stm32 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME stm32 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -54,7 +54,7 @@ if { [info exists BSTAPID ] } { set _BSTAPID4 0x06414041 # Connectivity line devices, Rev A and Rev Z set _BSTAPID5 0x06418041 -} +} jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 set _TARGETNAME $_CHIPNAME.cpu diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg index 39745717..215d12bb 100644 --- a/tcl/target/str710.cfg +++ b/tcl/target/str710.cfg @@ -1,21 +1,21 @@ #start slow, speed up after reset jtag_khz 10 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str710 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { set _CPUTAPID 0x3f0f0f0f } diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg index 53d7e1a1..d9e9ecf1 100644 --- a/tcl/target/str730.cfg +++ b/tcl/target/str730.cfg @@ -2,21 +2,21 @@ jtag_khz 3000 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str730 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { set _CPUTAPID 0x3f0f0f0f } diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg index 837f6b99..74f26642 100644 --- a/tcl/target/str750.cfg +++ b/tcl/target/str750.cfg @@ -1,20 +1,20 @@ #STR750 CPU -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str750 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { set _CPUTAPID 0x4f1f0041 } diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg index f0709eb4..b8f8f1ac 100644 --- a/tcl/target/str912.cfg +++ b/tcl/target/str912.cfg @@ -1,14 +1,14 @@ # script for str9 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str912 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -51,10 +51,10 @@ $_TARGETNAME configure -event reset-start { jtag_rclk 16 } $_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. #jtag_rclk 3000 - + # -- Enable 96K RAM # PFQBC enabled / DTCM & AHB wait-states disabled - mww 0x5C002034 0x0191 + mww 0x5C002034 0x0191 str9x flash_config 0 4 2 0 0x80000 flash protect 0 0 7 off diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg index cb28e632..836b2252 100644 --- a/tcl/target/telo.cfg +++ b/tcl/target/telo.cfg @@ -4,6 +4,6 @@ source [find c100.cfg] # it's really 16MB but the upper 8mb is controller via gpio? flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME -# +# gdb_memory_map enable diff --git a/tcl/target/test_reset_syntax_error.cfg b/tcl/target/test_reset_syntax_error.cfg index f2949e14..b8cfc62d 100644 --- a/tcl/target/test_reset_syntax_error.cfg +++ b/tcl/target/test_reset_syntax_error.cfg @@ -5,13 +5,13 @@ #jtag scan chain set _CHIPNAME syntaxtest -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf #target configuration set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 -$_TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { syntax error } diff --git a/tcl/target/test_syntax_error.cfg b/tcl/target/test_syntax_error.cfg index 8727aa36..d4f92fab 100644 --- a/tcl/target/test_syntax_error.cfg +++ b/tcl/target/test_syntax_error.cfg @@ -1,4 +1,4 @@ -# This script tests a syntax error in the startup +# This script tests a syntax error in the startup # config script syntax error here diff --git a/tcl/target/xba_revA3.cfg b/tcl/target/xba_revA3.cfg index 202ed608..0595fa16 100644 --- a/tcl/target/xba_revA3.cfg +++ b/tcl/target/xba_revA3.cfg @@ -1,14 +1,14 @@ #Written by: Michael Schwingen <rincewind@discworld.dascon.de> -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME xba_reva3 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # default to big endian set _ENDIAN big } @@ -81,7 +81,7 @@ $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-s flash bank cfi 0x50000000 0x400000 2 2 0 -init +init reset init # set big endian mode reg XSCALE_CTRL 0xF8 |