diff options
| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-25 18:29:17 +0100 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-25 22:15:57 +0100 |
| commit | a07422c26cb0a659c7615d6c0aa2cf09d8a48829 (patch) | |
| tree | 6acf5287811133833ae4f6eb641d5cc95a514eb9 /tcl/target | |
| parent | d785f552ee034aedb26aefc3e47e5c78cdcce065 (diff) | |
| download | openocd_libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.gz openocd_libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.bz2 openocd_libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.xz openocd_libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.zip | |
fix syntax of mww phys.
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/davinci.cfg | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index c14c98ea..ee840c8d 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -204,34 +204,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr $timer2_phys + 0x28] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - arm926ejs mww phys [expr $timer2_phys + 0x20] 0 + mww phys [expr $timer2_phys + 0x20] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - arm926ejs mww phys [expr $timer2_phys + 0x24] 0 - arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b + mww phys [expr $timer2_phys + 0x24] 0 + mww phys [expr $timer2_phys + 0x24] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - arm926ejs mww phys [expr $timer2_phys + 0x10] 0 - arm926ejs mww phys [expr $timer2_phys + 0x14] 0 - arm926ejs mww phys [expr $timer2_phys + 0x18] 0 - arm926ejs mww phys [expr $timer2_phys + 0x1c] 0 + mww phys [expr $timer2_phys + 0x10] 0 + mww phys [expr $timer2_phys + 0x14] 0 + mww phys [expr $timer2_phys + 0x18] 0 + mww phys [expr $timer2_phys + 0x1c] 0 # WDTCR: put into pre-active state, then active - arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000 + mww phys [expr $timer2_phys + 0x28] 0xa5c64000 + mww phys [expr $timer2_phys + 0x28] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr $timer2_phys + 0x28] 0x00004000 } |