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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-08-13 12:59:36 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-08-13 12:59:36 +0200 |
| commit | f60a2390cc5abe3d01633d9793ac1791fd0a3a5d (patch) | |
| tree | 00f146bd2b0bd651cf8e00bdd913f8200697b4f4 /tcl/target | |
| parent | dce422516ab1e28bb8045c9c081c73562dd1f163 (diff) | |
| download | openocd_libswd-f60a2390cc5abe3d01633d9793ac1791fd0a3a5d.tar.gz openocd_libswd-f60a2390cc5abe3d01633d9793ac1791fd0a3a5d.tar.bz2 openocd_libswd-f60a2390cc5abe3d01633d9793ac1791fd0a3a5d.tar.xz openocd_libswd-f60a2390cc5abe3d01633d9793ac1791fd0a3a5d.zip | |
lpc1768: turn down the jtag clock
Tests should that it needs to be as low as 100kHz to be
stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/lpc1768.cfg | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index ff92e4a7..07c5ab83 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -47,16 +47,18 @@ set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ lpc1700 $_CCLK calc_checksum -# JTAG clock should be CCLK/6 (unless using adaptive clocking) -# CCLK is 4 MHz after reset, and until board-specific code (like -# a reset-init handler) speeds it up. -# # Although rclk "appears to work", it turns out that this yields # 4MHz whereas the "correct" rate is CCLK/6, which is not what # you get with rclk. -jtag_khz [ expr 4000 / 6 ] - - +# +# Also, crank down the frequency further as we're running of an +# RC oscillator instead of crystal. +# +# Setting up XTAL in the reset-init sequence could be worth +# the effort if you need to program the flash which is pretty +# big on these devices. +# +jtag_khz 100 $_TARGETNAME configure -event reset-init { # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select |