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authorØyvind Harboe <oyvind.harboe@zylin.com>2009-10-09 09:14:27 +0200
committerØyvind Harboe <oyvind.harboe@zylin.com>2009-10-09 09:14:27 +0200
commit20a3b14828c5015647fa438e0cbee84685bcdf5f (patch)
treebda0e74286ee254951492546f2d883f0fbb81bd6 /tcl
parentbffe824df6f92a2e88932c9b6d01b26b3a0cc598 (diff)
parent60e24aa597cde2703e933759aebff5d3c2dde314 (diff)
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Merge commit 'origin/master'
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/pxa255.cfg35
1 files changed, 32 insertions, 3 deletions
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 1608d66c..7137621a 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -19,8 +19,37 @@ if { [info exists CPUTAPID ] } {
set _CPUTAPID 0x69264013
}
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-debug_level 3
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+ -chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+jtag_khz 300
+$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+ # assert both resets; equivalent to power-on reset
+ jtag_reset 1 1
+
+ # drop TRST after at least 32 cycles
+ sleep 1
+ jtag_reset 0 1
+
+ # minimum 32 TCK cycles to wake up the controller
+ runtest 50
+
+ # now the TAP will be responsive; validate scanchain
+ jtag arp_init
+
+ # ... and take it out of reset
+ jtag_reset 0 0
+}
+
+proc jtag_init {} {
+ init_reset startup
+}