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author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-10-05 08:20:28 +0000 |
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committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-10-05 08:20:28 +0000 |
commit | 7c7467b34f11939fbce41e39dfa1b6b0e110a89c (patch) | |
tree | 13b56b2b83316f8e2bc4e402c9d994cf858471fe /tcl | |
parent | 16a7ad5799ae488ad122648f2f74fe5d59e6c0c6 (diff) | |
download | openocd_libswd-7c7467b34f11939fbce41e39dfa1b6b0e110a89c.tar.gz openocd_libswd-7c7467b34f11939fbce41e39dfa1b6b0e110a89c.tar.bz2 openocd_libswd-7c7467b34f11939fbce41e39dfa1b6b0e110a89c.tar.xz openocd_libswd-7c7467b34f11939fbce41e39dfa1b6b0e110a89c.zip |
Add a new JTAG "setup" event; use for better DaVinci ICEpick support.
The model is that this fires after scanchain verification, when it's
safe to call "jtag tapenable $TAPNAME". So it will fire as part of
non-error paths of "init" and "reset" command processing. However it
will *NOT* trigger during "jtag_reset" processing, which skips all
scan chain verification, or after verification errors.
ALSO:
- switch DaVinci chips to use this new mechanism
- log TAP activation/deactivation, since their IDCODEs aren't verified
- unify "enum jtag_event" scripted event notifications
- remove duplicative JTAG_TAP_EVENT_POST_RESET
git-svn-id: svn://svn.berlios.de/openocd/trunk@2800 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/target/ti_dm355.cfg | 7 | ||||
-rw-r--r-- | tcl/target/ti_dm365.cfg | 20 | ||||
-rw-r--r-- | tcl/target/ti_dm6446.cfg | 22 |
3 files changed, 28 insertions, 21 deletions
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index b1e19e99..2551c3ed 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -9,11 +9,11 @@ if { [info exists CHIPNAME] } { # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* # after JTAG reset until ICEpick is used to route them in. -#set EMU01 "-disable" +set EMU01 "-disable" # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without # needing any ICEpick interaction. -set EMU01 "-enable" +#set EMU01 "-enable" source [find target/icepick.cfg] @@ -50,6 +50,9 @@ if { [info exists JRC_TAPID ] } { } jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + ################ # various symbol definitions, to avoid hard-wiring addresses diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index 3a17d1a8..e2d29bd5 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -7,16 +7,15 @@ if { [info exists CHIPNAME] } { set _CHIPNAME dm365 } -# -# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB -# are enabled without making ICEpick route ARM and ETB into the JTAG chain. -# -# Also note: when running without RTCK before the PLLs are set up, you -# may need to slow the JTAG clock down quite a lot (under 2 MHz). -# +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + source [find target/icepick.cfg] -set EMU01 "-enable" -#set EMU01 "-disable" # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer if { [info exists ETB_TAPID ] } { @@ -46,6 +45,9 @@ if { [info exists JRC_TAPID ] } { } jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + ################ # various symbol definitions, to avoid hard-wiring addresses diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg index e96c3e15..4dac3d5f 100644 --- a/tcl/target/ti_dm6446.cfg +++ b/tcl/target/ti_dm6446.cfg @@ -7,17 +7,15 @@ if { [info exists CHIPNAME] } { set _CHIPNAME dm6446 } -# -# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB -# are enabled without making ICEpick route ARM and ETB into the JTAG chain. -# Override by setting EMU01 to "-disable". -# -# Also note: when running without RTCK before the PLLs are set up, you -# may need to slow the JTAG clock down quite a lot (under 2 MHz). -# +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + source [find target/icepick.cfg] -set EMU01 "-enable" -#set EMU01 "-disable" # Subsidiary TAP: unknown ... must enable via ICEpick jtag newtap $_CHIPNAME unknown -irlen 8 -disable @@ -57,6 +55,10 @@ if { [info exists JRC_TAPID ] } { } jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) # and the ETB memory (4K) are other options, while trace is unused. # Little-endian; use the OpenOCD default. |