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authorAaron Carroll <aaronc@cse.unsw.edu.au>2011-02-02 18:16:26 +1100
committerØyvind Harboe <oyvind.harboe@zylin.com>2011-02-02 08:32:10 +0100
commitaaf145c42201496007e0fc9168d9738cb0237717 (patch)
tree5c6b5558c15583c8e214bfd3b25983bc1beac961 /tcl
parentefcea8306af922d867ff93073959dad774e10f0c (diff)
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omap4430: fix reset sequence
* Write to the PRM reset control register should have been 'phys'; * Setup empty reset-assert handlers for the M3's, since the board-level reset takes care of them; * Remove the dbginit cruft, because it gets called implicitly on reset. Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/omap4430.cfg11
1 files changed, 3 insertions, 8 deletions
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 360ac662..69678eec 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -92,15 +92,10 @@ jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.m31_dap
"
-proc omap4_dbginit {target} {
- # General Cortex A9 debug initialisation
- cortex_a9 dbginit
-}
-
-$_TARGETNAME configure -event reset-assert-post "omap4_dbginit $_TARGETNAME"
-
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
set PRM_RSTCTRL 0x4A307B00
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 0x1"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }