David Brownell <david-b@pacbell.net>:

Update the Beagle setup:

 - OMAP3530 updates:
    * split ICEpick TAP enable support to its own file, for
      reuse and eventually for storing other utility code
      like emulation reset
    * clean up, including labeling the tap as for DAP not
      for the Cortex-A8 and making endianness non-variable
    * add a few FIXMEs

 - BeagleBoard cleanup:  there's no SRST, "endstate" is gone, etc

I'm not sure I'd say it's further than "barely limping" just yet.
Key issues remain lack of Cortex-A8 support, and more complete
support for resetting.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2267 b42882b7-edfa-0310-969c-e2dbd0fdcd60

3 files changed, 73 insertions, 44 deletions

diff --git a/tcl/board/ti_beagleboard.cfg b/tcl/board/ti_beagleboard.cfg
index 170df460..9a789191 100644
--- a/tcl/board/ti_beagleboard.cfg
+++ b/tcl/board/ti_beagleboard.cfg
@@ -1,14 +1,9 @@
+# OMAP3 BeagleBoard
+#  http://beagleboard.org
 
 source [find target/omap3530.cfg]
 
-reset_config trst_and_srst
-jtag_reset 1 1
-sleep 10
-runtest 10
-jtag_reset 0 0
+# TI-14 JTAG connector
+reset_config trst_only
 
-endstate RUN/IDLE
-
-init
-
-omap3_dbginit
+# Later run:  omap3_dbginit
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
new file mode 100644
index 00000000..0597a9a5
--- /dev/null
+++ b/tcl/target/icepick.cfg
@@ -0,0 +1,23 @@
+# Utilities for TI ICEpick-C ... used in DaVinci, OMAP3, and more.
+
+# jrc	== TAP name for the ICEpick
+# port	== a port number, 0..15
+proc icepick_c_tapenable {jrc port} {
+
+	# NOTE:  it's important not to enter RUN/IDLE state until
+	# done sending these instructions and data to the ICEpick.
+	# And never to enter RESET, which will disable the TAPs.
+
+	# select router
+	irscan $jrc 7 -endstate IRPAUSE
+	drscan $jrc 8 0x89 -endstate DRPAUSE
+
+	# set ip control
+	irscan $jrc 2 -endstate IRPAUSE
+	drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
+
+	irscan $jrc 0x3F -endstate RUN/IDLE
+	runtest 10
+}
+
+# vim:syntax tcl
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index ad8f8ea8..aba6e255 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -1,57 +1,68 @@
-#File omap3530.cfg - as found on the BEAGLEBOARD
-#  Assumption is it is generic for all OMAP3530 
-
-#TI OMAP3 processor - http://www.ti.com 
+# TI OMAP3530
+#  http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# Other OMAP3 chips remove DSP and/or the OpenGL support
 
 if { [info exists CHIPNAME] } {	
    set  _CHIPNAME $CHIPNAME    
 } else {	 
-   set  _CHIPNAME omap3
+   set  _CHIPNAME omap3530
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-  # this defaults to a little endianness
-  set  _ENDIAN little
-}
+# ICEpick-C ... used to route Cortex, DSP, and more not shown here
+source [find target/icepick.cfg]
 
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID ] } {
+   set _DAP_TAPID $DAP_TAPID
 } else {
-  # force an error till we get a good number
-  set _CPUTAPID 0x0B6D602F
+   set _DAP_TAPID 0x0b6d602f
 }
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.dap -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
-
-target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
-
-jtag configure $_CHIPNAME.cpu -event tap-enable {
-	puts "Enabling Cortex-A8 @ OMAP3"
-	irscan omap3.jrc 7 -endstate IRPAUSE
-	drscan omap3.jrc 8 0x89 -endstate DRPAUSE
-	irscan omap3.jrc 2 -endstate IRPAUSE
-	drscan omap3.jrc 32 0xa3002108  -endstate RUN/IDLE
-	irscan omap3.jrc 0x3F -endstate RUN/IDLE
-	runtest 10
-	puts "Cortex-A8 @ OMAP3 enabled"
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID ] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7ae02f
 }
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID
+
+# GDB target:  Cortex-A8, using DAP
 
+# FIXME when we have A8 support, use it.  A8 != M3 ...
+target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
+
+# FIXME much of this should be in reset event handlers
 proc omap3_dbginit { } {
-     version
-     jtag tapenable omap3.cpu
+     reset
+     sleep 500
+
+     jtag tapenable omap3530.dap
      targets
      # sleep 1000
      # dap apsel 1
      # sleep 1000
      # dap apsel 1
      # dap info 1
-     omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
+
+     # 0xd401.0000 - ETM
+     # 0xd401.1000 - Cortex-A8
+     # 0xd401.9000 - TPIU (traceport)
+     # 0xd401.b000 - ETB
+     # 0xd401.d000 - DAPCTL
+
+     omap3.cpu mww 0x54011FB0 0xC5ACCE55
+
      omap3.cpu mdw 0x54011314
      omap3.cpu mdw 0x54011314
      # omap3.cpu mdw 0x54011080
-     omap3.cpu mww 0x5401d030 0x00002000 4
+
+     omap3.cpu mww 0x5401d030 0x00002000
 }