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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-10 11:43:48 +0000 |
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| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-10 11:43:48 +0000 |
| commit | 9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1 (patch) | |
| tree | 528bc639688200b05ae27df46046c3544399d121 /testing/examples/LPC2148Test/prj/eclipse_ram.gdb | |
| parent | 1ade331ba925c506ed4254f31dba5e6f9cf782b4 (diff) | |
| download | openocd_libswd-9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1.tar.gz openocd_libswd-9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1.tar.bz2 openocd_libswd-9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1.tar.xz openocd_libswd-9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1.zip | |
- single core context used, removed debug context as thought unnecessary.
- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit
git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'testing/examples/LPC2148Test/prj/eclipse_ram.gdb')
0 files changed, 0 insertions, 0 deletions