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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-20 07:15:46 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-20 07:15:46 +0000 |
| commit | 028e535604bf52761115c81ed65c07d0a4a64cd0 (patch) | |
| tree | 9ad3f04947ab21933d91de176b5f8ed4ffd025c6 /testing/examples/LPC2148Test/test_ram.hex | |
| parent | c2f593bdc1dd683fdd11800e40e9f71f5729c6ba (diff) | |
| download | openocd_libswd-028e535604bf52761115c81ed65c07d0a4a64cd0.tar.gz openocd_libswd-028e535604bf52761115c81ed65c07d0a4a64cd0.tar.bz2 openocd_libswd-028e535604bf52761115c81ed65c07d0a4a64cd0.tar.xz openocd_libswd-028e535604bf52761115c81ed65c07d0a4a64cd0.zip | |
David Brownell <david-b@pacbell.net>More Thumb2 disassembly:
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler. LDREX and STREX are not
issued by GCC without inline assembly.
This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled. Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'testing/examples/LPC2148Test/test_ram.hex')
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