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authorddraskovic <ddraskovic@sequans.com>2010-11-04 14:33:10 +0100
committerØyvind Harboe <oyvind.harboe@zylin.com>2010-11-04 14:52:47 +0100
commit9e3d43cfe75df7c4f6797d630576f1a02428b218 (patch)
treec331246ddc8cd9b14131ab4f0c5bdb16ee69dae4 /testing/examples/SAM7S256Test/test_rom.elf
parent70b15389962637f13f5f3f10a6beebabed419c69 (diff)
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arm964e: Add support for ARM946E target.
So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
Diffstat (limited to 'testing/examples/SAM7S256Test/test_rom.elf')
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