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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-25 20:02:19 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-25 20:02:19 +0000 |
| commit | bc075606b7de9f85bff50e8afc0dbdcba3a99765 (patch) | |
| tree | 56bb23600c16113d7cefdb36265e9b482222370b /testing/examples/SAM7X256Test/test_ram.hex | |
| parent | 24f011ebb49dea93110c0fbafc882990f9f05cc7 (diff) | |
| download | openocd_libswd-bc075606b7de9f85bff50e8afc0dbdcba3a99765.tar.gz openocd_libswd-bc075606b7de9f85bff50e8afc0dbdcba3a99765.tar.bz2 openocd_libswd-bc075606b7de9f85bff50e8afc0dbdcba3a99765.tar.xz openocd_libswd-bc075606b7de9f85bff50e8afc0dbdcba3a99765.zip | |
David Brownell <david-b@pacbell.net> Tweak disassembly commands:
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'testing/examples/SAM7X256Test/test_ram.hex')
0 files changed, 0 insertions, 0 deletions