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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 21:24:44 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 21:24:44 -0800 |
| commit | b6210907ea584095cdede663f695eb8afeecef14 (patch) | |
| tree | 13844914f68dc154959a27c914e9160ceb658817 /testing/examples/SAM7X256Test/test_ram.map | |
| parent | e109bb6af211d3916e4006127945d128b138529b (diff) | |
| download | openocd_libswd-b6210907ea584095cdede663f695eb8afeecef14.tar.gz openocd_libswd-b6210907ea584095cdede663f695eb8afeecef14.tar.bz2 openocd_libswd-b6210907ea584095cdede663f695eb8afeecef14.tar.xz openocd_libswd-b6210907ea584095cdede663f695eb8afeecef14.zip | |
Cortex-A8: avoid DSCR reads
There was a lot of needless handshaking overhead in the current
Cortex-A8 DCC/ITR operations, since the status read by each step
was discarded rather than letting the next step know it.
This shrinks the handshaking by: (a) passing status along from
previous steps, avoiding re-fetching; which enables the big win
(b) relying on a useful invariant: that the DSCR_INSTR_COMP bit
is set after every call to a DPM method.
A "reg sp_usr" call previously took 17 flushes; now it takes just 9.
This visibly speeds common operations like entry to debug state and
stepping, as well as "arm reg" and so on.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'testing/examples/SAM7X256Test/test_ram.map')
0 files changed, 0 insertions, 0 deletions