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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-07 14:46:29 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-07 14:57:43 -0800 |
| commit | 7936ab16da93f91258e17e4699360dc3f43728ce (patch) | |
| tree | 75e92bb7d1f8fe9926095b6e59ba4617ff64a31c /testing/examples/STR912Test/test_ram.map | |
| parent | efb93efd6f2eb7aa555e4e86e95b636003ccf37a (diff) | |
| download | openocd_libswd-7936ab16da93f91258e17e4699360dc3f43728ce.tar.gz openocd_libswd-7936ab16da93f91258e17e4699360dc3f43728ce.tar.bz2 openocd_libswd-7936ab16da93f91258e17e4699360dc3f43728ce.tar.xz openocd_libswd-7936ab16da93f91258e17e4699360dc3f43728ce.zip | |
ARM: disassemble two more v6+ instructions
The SRS and RFE instructions speed exception entry/exit by
making it easy to save and restore PC and SPSR. This handles
both ARM and Thumb2 encodings.
Fix minor PLD goofage; that "should never reach this point"
can't happen, so remove it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'testing/examples/STR912Test/test_ram.map')
0 files changed, 0 insertions, 0 deletions