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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 13:23:00 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 13:23:00 -0800 |
| commit | 8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 (patch) | |
| tree | 03fec2659ca4d6611168ab8d6eb100019a3204d1 /testing/examples | |
| parent | bbebfd9e134ec84a29dd68bc3661ead57435a4c3 (diff) | |
| download | openocd_libswd-8a6d4ced4c0d17626c3875d5f8819efa3ac0f155.tar.gz openocd_libswd-8a6d4ced4c0d17626c3875d5f8819efa3ac0f155.tar.bz2 openocd_libswd-8a6d4ced4c0d17626c3875d5f8819efa3ac0f155.tar.xz openocd_libswd-8a6d4ced4c0d17626c3875d5f8819efa3ac0f155.zip | |
ARM: setup "secure monitor mode" shadow regs
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'testing/examples')
0 files changed, 0 insertions, 0 deletions