diff options
| -rw-r--r-- | src/target/armv7a.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 5d3976f5..e889a8a1 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -98,22 +98,16 @@ int armv7a_arch_state(struct target *target) return ERROR_INVALID_ARGUMENTS; } - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, - target->debug_reason)->name, - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + armv4_5_arch_state(target); + + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[armv7a->armv4_5_mmu.mmu_enabled], state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); if (armv4_5->core_mode == ARMV4_5_MODE_ABT) armv7a_show_fault_registers(target); - else if (target->debug_reason == DBG_REASON_WATCHPOINT) + if (target->debug_reason == DBG_REASON_WATCHPOINT) LOG_USER("Watchpoint triggered at PC %#08x", (unsigned) armv7a->dpm.wp_pc); |