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-rw-r--r--src/target/cortex_m3.c14
-rw-r--r--src/target/cortex_m3.h6
2 files changed, 4 insertions, 16 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index ef57a4cd..d8a28796 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1495,7 +1495,7 @@ static int cortex_m3_init_target(struct command_context_s *cmd_ctx,
static int cortex_m3_examine(struct target_s *target)
{
int retval;
- uint32_t cpuid, fpcr, dwtcr, ictr;
+ uint32_t cpuid, fpcr, dwtcr;
int i;
/* get pointers to arch-specific information */
@@ -1511,21 +1511,15 @@ static int cortex_m3_examine(struct target_s *target)
target_set_examined(target);
/* Read from Device Identification Registers */
- if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK)
+ retval = target_read_u32(target, CPUID, &cpuid);
+ if (retval != ERROR_OK)
return retval;
if (((cpuid >> 4) & 0xc3f) == 0xc23)
LOG_DEBUG("CORTEX-M3 processor detected");
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- target_read_u32(target, NVIC_ICTR, &ictr);
- cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
- cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
- for (i = 0; i < cortex_m3->intlinesnum; i++)
- {
- target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
- LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]);
- }
+ /* NOTE: FPB and DWT are both optional. */
/* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr);
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index f4cefa78..a7074d36 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -60,8 +60,6 @@
#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
-#define DWT_CTRL 0xE0001000
-
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
@@ -160,10 +158,6 @@ typedef struct cortex_m3_common_s
int dwt_comp_available;
cortex_m3_dwt_comparator_t *dwt_comparator_list;
- /* Interrupts */
- int intlinesnum;
- uint32_t *intsetenable;
-
armv7m_common_t armv7m;
void *arch_info;
} cortex_m3_common_t;