diff options
| -rw-r--r-- | tcl/board/da850evm.cfg | 10 | ||||
| -rw-r--r-- | tcl/target/omapl138.cfg | 66 |
2 files changed, 76 insertions, 0 deletions
diff --git a/tcl/board/da850evm.cfg b/tcl/board/da850evm.cfg new file mode 100644 index 00000000..fbec6092 --- /dev/null +++ b/tcl/board/da850evm.cfg @@ -0,0 +1,10 @@ +#DA850 EVM board +# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939 +# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit + +source [find target/omapl138.cfg] + +reset_config trst_and_srst separate + +#currently any pinmux/timing must be setup by UBL before openocd can do debug +#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg new file mode 100644 index 00000000..6e06a193 --- /dev/null +++ b/tcl/target/omapl138.cfg @@ -0,0 +1,66 @@ +# +# Texas Instruments DaVinci family: OMAPL138 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omapl138 +} + +source [find target/icepick.cfg] + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID ] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable +jtag configure $_CHIPNAME.etb -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 3" + +# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID ] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07926001 +} +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable +jtag configure $_CHIPNAME.arm -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 2" + +# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID ] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b7d102f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) +# and the ETB memory (4K) are other options, while trace is unused. +# Little-endian; use the OpenOCD default. +set _TARGETNAME $_CHIPNAME.arm + +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 + +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +jtag_rclk 1500 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 } + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb + +gdb_breakpoint_override hard +arm7_9 dbgrq enable |