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-rw-r--r--src/target/target/pxa255.cfg172
1 files changed, 86 insertions, 86 deletions
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg
index 6666309d..2a452135 100644
--- a/src/target/target/pxa255.cfg
+++ b/src/target/target/pxa255.cfg
@@ -1,86 +1,86 @@
-jtag_device 5 0x1 0x1f 0x1e
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-target xscale little reset_init 0 pxa255
-reset_config trst_and_srst
-run_and_halt_time 0 30
-
-target_script 0 reset /ram/pxa255.init
-
-#xscale debug_handler 0 0xFFFF0800 # debug handler base address
-
-trunc /ram/pxa255.init
-append /ram/pxa255.init #configuration file for PXA250 Evaluation Board
-append /ram/pxa255.init # -----------------------------------------------------
-append /ram/pxa255.init #
-append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
-append /ram/pxa255.init #
-append /ram/pxa255.init # setup GPIO
-append /ram/pxa255.init #
-append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init
-append /ram/pxa255.init
-append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init
-append /ram/pxa255.init #
-append /ram/pxa255.init # setup memory controller
-append /ram/pxa255.init #
-append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init #
-append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init
-append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS
-append /ram/pxa255.init sleep 20
-append /ram/pxa255.init
+jtag_device 5 0x1 0x1f 0x1e
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+target xscale little reset_init 0 pxa255
+reset_config trst_and_srst
+run_and_halt_time 0 30
+
+target_script 0 reset /ram/pxa255.init
+
+#xscale debug_handler 0 0xFFFF0800 # debug handler base address
+
+trunc /ram/pxa255.init
+append /ram/pxa255.init #configuration file for PXA250 Evaluation Board
+append /ram/pxa255.init # -----------------------------------------------------
+append /ram/pxa255.init #
+append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
+append /ram/pxa255.init #
+append /ram/pxa255.init # setup GPIO
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init
+append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init #
+append /ram/pxa255.init # setup memory controller
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
generated by cgit v1.2.3 (git 2.46.0) at 2025-01-11 07:32:51 +0000