diff options
Diffstat (limited to 'src/target/target/pxa270.cfg')
| -rw-r--r-- | src/target/target/pxa270.cfg | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg index 5946e757..549555de 100644 --- a/src/target/target/pxa270.cfg +++ b/src/target/target/pxa270.cfg @@ -1,22 +1,22 @@ -#Marvell/Intel PXA270 Script
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 260
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-#use combined on interfaces or targets that can’t set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-#target configuration
-daemon_startup reset
-target xscale little reset_halt 0 pxa27x
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-working_area 0 0x5c000000 0x10000 nobackup
-run_and_halt_time 0 30
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x1000000 2 4 0
+#Marvell/Intel PXA270 Script +# set jtag_nsrst_delay to the delay introduced by your reset circuit +# the rest of the needed delays are built into the openocd program +jtag_nsrst_delay 260 +# set the jtag_ntrst_delay to the delay introduced by a reset circuit +# the rest of the needed delays are built into the openocd program +jtag_ntrst_delay 0 +#use combined on interfaces or targets that can’t set TRST/SRST separately +reset_config trst_and_srst separate +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 7 0x1 0x7f 0x7e +#target configuration +daemon_startup reset +target xscale little reset_halt 0 pxa27x +# maps to PXA internal RAM. If you are using a PXA255 +# you must initialize SDRAM or leave this option off +working_area 0 0x5c000000 0x10000 nobackup +run_and_halt_time 0 30 +#flash bank <driver> <base> <size> <chip_width> <bus_width> +# works for P30 flash +flash bank cfi 0x00000000 0x1000000 2 4 0 |