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-rw-r--r--src/target/cortex_a9.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/target/cortex_a9.c b/src/target/cortex_a9.c
index 3ad7a7d3..422da3f7 100644
--- a/src/target/cortex_a9.c
+++ b/src/target/cortex_a9.c
@@ -1521,6 +1521,7 @@ static int cortex_a9_read_phys_memory(struct target *target,
uint32_t saved_r0, saved_r1;
int nbytes = count * size;
uint32_t data;
+ int enabled = 0;
if (target->state != TARGET_HALTED)
{
@@ -1528,6 +1529,16 @@ static int cortex_a9_read_phys_memory(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
+ retval = cortex_a9_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (enabled)
+ {
+ LOG_WARNING("Reading physical memory through APB with MMU enabled is not yet implemented");
+ return ERROR_TARGET_FAILURE;
+ }
+
/* save registers r0 and r1, we are going to corrupt them */
retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r0, 0);
if (retval != ERROR_OK)
@@ -1635,6 +1646,7 @@ static int cortex_a9_write_phys_memory(struct target *target,
uint32_t saved_r0, saved_r1;
int nbytes = count * size;
uint32_t data;
+ int enabled = 0;
if (target->state != TARGET_HALTED)
{
@@ -1642,6 +1654,16 @@ static int cortex_a9_write_phys_memory(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
+ retval = cortex_a9_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (enabled)
+ {
+ LOG_WARNING("Writing physical memory through APB with MMU enabled is not yet implemented");
+ return ERROR_TARGET_FAILURE;
+ }
+
/* save registers r0 and r1, we are going to corrupt them */
retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r0, 0);
if (retval != ERROR_OK)