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-rw-r--r--src/target/target/pxa270.cfg11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg
index 68e7ffc3..34bb60d4 100644
--- a/src/target/target/pxa270.cfg
+++ b/src/target/target/pxa270.cfg
@@ -12,6 +12,9 @@ if { [info exists ENDIAN] } {
set _ENDIAN little
}
+#IDs for pxa270. Choose one. Are there others?#
+#set CPUTAPID 0x79265013
+#set CPUTAPID 0x49265013
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -26,10 +29,6 @@ jtag_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
@@ -38,7 +37,3 @@ target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
# maps to PXA internal RAM. If you are using a PXA255
# you must initialize SDRAM or leave this option off
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x1000000 2 4 0