summaryrefslogtreecommitdiff
path: root/src/target
diff options
context:
space:
mode:
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm7_9_common.c22
-rw-r--r--src/target/arm_adi_v5.c32
-rw-r--r--src/target/armv4_5.c2
-rw-r--r--src/target/cortex_m3.c8
-rw-r--r--src/target/etm.c4
-rw-r--r--src/target/mips32.h4
-rw-r--r--src/target/target.c4
-rw-r--r--src/target/xscale.c2
8 files changed, 39 insertions, 39 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index e8023c86..1b08d474 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1951,7 +1951,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
@@ -2842,17 +2842,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr | spsr>");
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
- COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
+ COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
- COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable|disable>");
+ COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
- COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
+ COMMAND_ANY, "use DCC downloads for larger memory writes <enable | disable>");
armv4_5_register_commands(cmd_ctx);
@@ -2884,7 +2884,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
if (argc < 2)
{
- command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
+ command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr | spsr>");
return ERROR_OK;
}
@@ -2929,7 +2929,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
if (argc < 3)
{
- command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
+ command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
return ERROR_OK;
}
@@ -3005,7 +3005,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
+ command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable | disable>");
}
}
@@ -3038,7 +3038,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
+ command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable | disable>");
}
}
@@ -3071,7 +3071,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
+ command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable | disable>");
}
}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 126d9557..a77daa70 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1068,11 +1068,11 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
command_print(cmd_ctx, "\tROM table in legacy format" );
}
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
swjdp_transaction_endcheck(swjdp);
command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
if (memtype&0x01)
@@ -1084,25 +1084,25 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
}
- /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
+ /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
+ mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3);
component_start = component_base - 0x1000*(c_pid4 >> 4);
command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 33f1a518..77ca2e25 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -456,7 +456,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
- register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
+ register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm | thumb>");
register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
return ERROR_OK;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index c1ebae3f..9f4ef523 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1112,8 +1112,8 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
comparator_list[dwt_num].mask = mask;
comparator_list[dwt_num].function = watchpoint->rw + 5;
target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
}
else
@@ -1149,7 +1149,7 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint
}
comparator_list[dwt_num].used = 0;
comparator_list[dwt_num].function = 0;
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
watchpoint->set = 0;
@@ -1648,7 +1648,7 @@ int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
{
if (!strcmp(args[0], "on"))
{
- cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0);
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
}
else if (!strcmp(args[0], "off"))
{
diff --git a/src/target/etm.c b/src/target/etm.c
index 44ae9304..48d2ebaf 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1107,7 +1107,7 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
}
else if (argc != 0)
{
- command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
+ command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
return ERROR_OK;
}
@@ -1826,7 +1826,7 @@ int etm_register_commands(struct command_context_s *cmd_ctx)
int etm_register_user_commands(struct command_context_s *cmd_ctx)
{
register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
- COMMAND_EXEC, "configure trace mode <none|data|address|all> "
+ COMMAND_EXEC, "configure trace mode <none | data | address | all> "
"<context_id_bits> <cycle_accurate> <branch_output>");
register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
diff --git a/src/target/mips32.h b/src/target/mips32.h
index ab47f731..33f0c833 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -94,8 +94,8 @@ typedef struct mips32_core_reg_s
#define MIPS32_COP0_MF 0x00
#define MIPS32_COP0_MT 0x04
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|((rd) << 11)| ((shamt) << 6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|(immd))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
#define MIPS32_NOP 0
diff --git a/src/target/target.c b/src/target/target.c
index ca21f7f6..5433316a 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1483,7 +1483,7 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, NULL, "halt", handle_halt_command, COMMAND_EXEC, "halt target");
register_command(cmd_ctx, NULL, "resume", handle_resume_command, COMMAND_EXEC, "resume target [addr]");
register_command(cmd_ctx, NULL, "step", handle_step_command, COMMAND_EXEC, "step one instruction from current PC or [addr]");
- register_command(cmd_ctx, NULL, "reset", handle_reset_command, COMMAND_EXEC, "reset target [run|halt|init] - default is run");
+ register_command(cmd_ctx, NULL, "reset", handle_reset_command, COMMAND_EXEC, "reset target [run | halt | init] - default is run");
register_command(cmd_ctx, NULL, "soft_reset_halt", handle_soft_reset_halt_command, COMMAND_EXEC, "halt the target and do a soft reset");
register_command(cmd_ctx, NULL, "mdw", handle_md_command, COMMAND_EXEC, "display memory words <addr> [count]");
@@ -3987,7 +3987,7 @@ static int tcl_target_func( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
break;
case TS_CMD_RESET:
if ( goi.argc != 2 ){
- Jim_WrongNumArgs( interp, 2, argv, "t|f|assert|deassert BOOL");
+ Jim_WrongNumArgs( interp, 2, argv, "t | f|assert | deassert BOOL");
return JIM_ERR;
}
e = Jim_GetOpt_Nvp( &goi, nvp_assert, &n );
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 8c206537..e87f5527 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3693,7 +3693,7 @@ int xscale_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
- register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
+ register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-23 15:06:57 +0000