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-rw-r--r--tcl/target/at91sam9260_ext_RAM_ext_flash.cfg6
-rw-r--r--tcl/target/c100.cfg2
-rw-r--r--tcl/target/c100helper.tcl2
-rw-r--r--tcl/target/dsp56321.cfg2
-rw-r--r--tcl/target/lm3s6965.cfg2
-rw-r--r--tcl/target/lpc2124.cfg2
-rw-r--r--tcl/target/lpc2378.cfg2
-rw-r--r--tcl/target/mc13224v.cfg2
-rw-r--r--tcl/target/mega128.cfg4
-rw-r--r--tcl/target/pxa255.cfg4
-rw-r--r--tcl/target/readme.txt6
-rw-r--r--tcl/target/samsung_s3c2450.cfg4
-rw-r--r--tcl/target/stellaris.cfg4
-rw-r--r--tcl/target/stm32.cfg2
-rw-r--r--tcl/target/str710.cfg6
-rw-r--r--tcl/target/str730.cfg6
-rw-r--r--tcl/target/str750.cfg6
-rw-r--r--tcl/target/telo.cfg8
18 files changed, 35 insertions, 35 deletions
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index 690406bb..03595404 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -1,7 +1,7 @@
-jtag_khz 4
+adapter_khz 4
######################################
@@ -62,7 +62,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
proc at91sam_init { } {
# at reset chip runs at 32khz
- jtag_khz 8
+ adapter_khz 8
halt
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
@@ -79,7 +79,7 @@ proc at91sam_init { } {
sleep 10 # wait 10 ms
# Now run at anything fast... ie: 10mhz!
- jtag_khz 10000 # Increase JTAG Speed to 6 MHz
+ adapter_khz 10000 # Increase JTAG Speed to 6 MHz
arm7_9 dcc_downloads enable # Enable faster DCC downloads
mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index b175f23f..23eca0c7 100644
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -3,7 +3,7 @@
# this script only configures one core (that is used to run Linux)
# assume no PLL lock, start slowly
-jtag_khz 100
+adapter_khz 100
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 96588713..1fd58b65 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -504,7 +504,7 @@ proc reboot {} {
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
puts "JTAG speed lowered to 100kHz"
- jtag_khz 100
+ adapter_khz 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."
diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 45068370..281c4ddd 100644
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID ] } {
}
#jtag speed
-jtag_khz 4500
+adapter_khz 4500
#has only srst
reset_config srst_only
diff --git a/tcl/target/lm3s6965.cfg b/tcl/target/lm3s6965.cfg
index 02d85d46..c6e623ee 100644
--- a/tcl/target/lm3s6965.cfg
+++ b/tcl/target/lm3s6965.cfg
@@ -13,7 +13,7 @@ if { [info exists CPUTAPID ] } {
}
# jtag speed
-jtag_khz 500
+adapter_khz 500
jtag_nsrst_delay 100
jtag_ntrst_delay 100
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 9a27aece..ce55952a 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -27,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-jtag_khz 1000
+adapter_khz 1000
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 4e50ac5c..7eb0dabb 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -47,4 +47,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
# 4MHz / 6 = 666kHz, so use 500
-jtag_khz 500
+adapter_khz 500
diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 497e376e..33351caf 100644
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -36,7 +36,7 @@ jtag_ntrst_delay 200
# rclk hasn't been working well. This maybe the mc13224v or something else.
#jtag_rclk 2000
-jtag_khz 2000
+adapter_khz 2000
######################
# Target configuration
diff --git a/tcl/target/mega128.cfg b/tcl/target/mega128.cfg
index 2cf31d61..697ec45b 100644
--- a/tcl/target/mega128.cfg
+++ b/tcl/target/mega128.cfg
@@ -4,7 +4,7 @@
set _ENDIAN little
# jtag speed
-jtag_khz 4500
+adapter_khz 4500
reset_config srst_only
jtag_nsrst_delay 100
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
#to use it, script will be like:
#init
-#jtag_khz 4500
+#adapter_khz 4500
#reset init
#verify_ircapture disable
#
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 44efdaa4..5b745f85 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt
index 39f8d124..f028b11c 100644
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled.
flash write_image [file] <parameters>
verify_image [file] <parameters>
-4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
multiple times only the last setting is used.
interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any jtag_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter_khz in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
set the default JTAG speed.
Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg
index 071b271a..00754260 100644
--- a/tcl/target/samsung_s3c2450.cfg
+++ b/tcl/target/samsung_s3c2450.cfg
@@ -7,11 +7,11 @@
#
# RCLK?
#
-# jtag_khz 0
+# adapter_khz 0
#
# Really low clock during reset?
#
-# jtag_khz 1
+# adapter_khz 1
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 6fafac94..5f4428f5 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -41,8 +41,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
# NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
-jtag_khz 500
-$_TARGETNAME configure -event reset-start {jtag_khz 500}
+adapter_khz 500
+$_TARGETNAME configure -event reset-start {adapter_khz 500}
# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg
index 463a85cf..29c9f7ff 100644
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -21,7 +21,7 @@ if { [info exists WORKAREASIZE] } {
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-jtag_khz 1000
+adapter_khz 1000
jtag_nsrst_delay 100
jtag_ntrst_delay 100
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index 028c6043..4d685865 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -1,5 +1,5 @@
#start slow, speed up after reset
-jtag_khz 10
+adapter_khz 10
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
- jtag_khz 6000
+ adapter_khz 6000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 09179531..3a84897c 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -1,6 +1,6 @@
#STR730 CPU
-jtag_khz 3000
+adapter_khz 3000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -33,9 +33,9 @@ jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
- jtag_khz 3000
+ adapter_khz 3000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index c467ae25..c2fb7869 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
}
# jtag speed
-jtag_khz 10
+adapter_khz 10
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
@@ -35,9 +35,9 @@ jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
- jtag_khz 3000
+ adapter_khz 3000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg
index 0cbdb816..99b9cd69 100644
--- a/tcl/target/telo.cfg
+++ b/tcl/target/telo.cfg
@@ -26,12 +26,12 @@ reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
- jtag_khz 100
+ adapter_khz 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
- jtag_khz 3000
- puts "JTAG speek now 3MHz"
+ adapter_khz 3000
+ puts "JTAG speed now 3MHz"
puts "type helpC100 to get help on C100"
}
@@ -58,4 +58,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
# writing data to memory does not work without this
-memwrite burst disable \ No newline at end of file
+memwrite burst disable
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-23 09:25:23 +0000