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+<html>
+<head>
+<title>Test results for version 1.62</title>
+</head>
+
+<body>
+
+<H1>STR912</H1>
+
+<H2>Connectivity</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="CON001"/>CON001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Telnet connection</td>
+ <td>Power on, jtag target attached</td>
+ <td>On console, type<br><code>telnet ip port</code></td>
+ <td><code>Open On-Chip Debugger<br>></code></td>
+ <td><code>> telnet 10.0.0.142<br>
+ Trying 10.0.0.142...<br>
+ Connected to 10.0.0.142.<br>
+ Escape character is '^]'.<br>
+ Open On-Chip Debugger<br>
+ >
+</code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="CON002"/>CON002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>GDB server connection</td>
+ <td>Power on, jtag target attached</td>
+ <td>On GDB console, type<br><code>target remote ip:port</code></td>
+ <td><code>Remote debugging using 10.0.0.73:3333</code></td>
+ <td><code>
+ (gdb) tar remo 10.0.0.142:3333<br>
+ Remote debugging using 10.0.0.142:3333<br>
+ 0x00016434 in ?? ()<br>
+ (gdb)
+ </code></td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+<H2>Reset</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="RES001"/>RES001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Reset halt on a blank target</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+ <td>
+ <code>
+> reset halt<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RES002"/>RES002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Reset init on a blank target</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset init</code></td>
+ <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
+ <td>
+ <code>
+> reset init<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+cleared protection for sectors 0 through 7 on flash bank 0<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RES003"/>RES003</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Reset after a power cycle of the target</td>
+ <td>Reset the target then power cycle the target</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+ <td>
+ <code>
+ nsed nSRST asserted.<br>
+ nsed power dropout.<br>
+ nsed power restore.<br>
+RCLK - adaptive<br>
+SRST took 85ms to deassert<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+cleared protection for sectors 0 through 7 on flash bank 0<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+> reset halt<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RES004"/>RES004</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Reset halt on a blank target where reset halt is supported</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+ <td>
+ <code>
+> reset halt<br>
+ RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)<br>
+JTAG Tap/device matched<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (Manufacturer: 0x020, Part: 0x5966, Version: 0x2)<br>
+JTAG Tap/device matched<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (Manufacturer: 0x020, Part: 0x457f, Version: 0x2)<br>
+JTAG Tap/device matched<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RES005"/>RES005</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Reset halt on a blank target using return clock</td>
+ <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+ <td>
+ <code>
+ > reset halt<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+<H2>JTAG Speed</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>ZY1000</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="SPD001"/>SPD001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>16MHz on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>
+ <code>
+> jtag_khz 16000<br>
+jtag_speed 4 => JTAG clk=16.000000<br>
+16000 kHz<br>
+ThumbEE -- incomplete support<br>
+target state: halted<br>
+target halted in ThumbEE state due to debug-request, current mode: System<br>
+cpsr: 0xfdfdffff pc: 0xfdfdfff9<br>
+> mdw 0 32 <br>
+0x00000000: 00000000 00000000 ffffffff ffffffff 00000001 ffffffff 00000001 ffffffff<br>
+0x00000020: 00000001 00000001 00000001 00000001 00000001 fffffffe fffffffe 00000001<br>
+0x00000040: fffffffe 00000000 00000000 00000000 00000000 00000000 00000000 00000000<br>
+0x00000060: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000001 00000000<br>
+invalid mode value encountered 0<br>
+cpsr contains invalid mode value - communication failure<br>
+ThumbEE -- incomplete support<br>
+target state: halted<br>
+target halted in ThumbEE state due to debug-request, current mode: System<br>
+cpsr: 0xffffffff pc: 0xfffffff8<br>
+>
+ </code>
+ </td>
+ <td><font color=red><b>FAIL</b></font></td>
+ </tr>
+ <tr>
+ <td><a name="SPD002"/>SPD002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>8MHz on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>
+ <code>
+> jtag_khz 8000<br>
+jtag_speed 8 => JTAG clk=8.000000<br>
+8000 kHz<br>
+> halt <br>
+invalid mode value encountered 0<br>
+cpsr contains invalid mode value - communication failure<br>
+Command handler execution failed<br>
+in procedure 'halt' called at file "command.c", line 647<br>
+called at file "command.c", line 361<br>
+Halt timed out, wake up GDB.<br>
+>
+ </code>
+ </td>
+ <td><font color=red><b>FAIL</b></font></td>
+ </tr>
+ <tr>
+ <td><a name="SPD003"/>SPD003</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>4MHz on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>
+ <code>
+> jtag_khz 4000<br>
+jtag_speed 16 => JTAG clk=4.000000<br>
+4000 kHz<br>
+> halt <br>
+> mdw 0 32 <br>
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="SPD004"/>SPD004</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>2MHz on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>
+ <code>
+> jtag_khz 2000<br>
+jtag_speed 32 => JTAG clk=2.000000<br>
+2000 kHz<br>
+> halt<br>
+> mdw 0 32<br>
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="SPD005"/>SPD005</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>RCLK on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>
+ <code>
+> jtag_khz 0<br>
+RCLK - adaptive<br>
+> halt <br>
+> mdw 0 32 <br>
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+<H2>Debugging</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="DBG001"/>DBG001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Load is working</td>
+ <td>Reset init is working, RAM is accesible, GDB server is started</td>
+ <td>On the console of the OS: <br>
+ <code>arm-elf-gdb test_ram.elf</code><br>
+ <code>(gdb) target remote ip:port</code><br>
+ <code>(gdb) load</load>
+ </td>
+ <td>Load should return without error, typical output looks like:<br>
+ <code>
+ Loading section .text, size 0x14c lma 0x0<br>
+ Start address 0x40, load size 332<br>
+ Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
+ </code>
+ </td>
+ <td><code>
+(gdb) load<br>
+Loading section .text, size 0x1a0 lma 0x4000000<br>
+Loading section .rodata, size 0x4 lma 0x40001a0<br>
+Start address 0x4000000, load size 420<br>
+Transfer rate: 29 KB/sec, 210 bytes/write.<br>
+(gdb)
+ </code></td>
+ <td>PASS</td>
+ </tr>
+
+ <tr>
+ <td><a name="DBG002"/>DBG002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Software breakpoint</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001</td>
+ <td>In the GDB console:<br>
+ <code>
+ (gdb) monitor gdb_breakpoint_override soft<br>
+ force soft breakpoints<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
+ (gdb) continue<br>
+ Continuing.
+ </code>
+ </td>
+ <td>The software breakpoint should be reached, a typical output looks like:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+ cpsr: 0x000000d3 pc: 0x000000ec<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:71<br>
+ 71 DWORD a = 1;
+ </code>
+ </td>
+ <td>
+ <code>
+(gdb) monitor gdb_breakpoint_override soft<br>
+force soft breakpoints<br>
+Current language: auto<br>
+The current source language is "auto; currently asm".<br>
+(gdb) break main<br>
+Breakpoint 1 at 0x4000144: file src/main.c, line 69.<br>
+(gdb) c<br>
+Continuing.<br>
+<br>
+Breakpoint 1, main () at src/main.c:69<br>
+warning: Source file is more recent than executable.<br>
+69 DWORD a = 1;<br>
+Current language: auto<br>
+The current source language is "auto; currently c".<br>
+(gdb)
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="DBG003"/>DBG003</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Single step in a RAM application</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+ <td>In GDB, type <br><code>(gdb) step</code></td>
+ <td>The next instruction should be reached, typical output:<br>
+ <code>
+ (gdb) step<br>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Abort<br>
+ cpsr: 0x20000097 pc: 0x000000f0<br>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Abort<br>
+ cpsr: 0x20000097 pc: 0x000000f4<br>
+ 72 DWORD b = 2;
+ </code>
+ </td>
+ <td>
+ <code>
+ (gdb) step<br>
+ 70 DWORD b = 2;<br>
+ (gdb)<br>
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="DBG004"/>DBG004</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Software break points are working after a reset</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+ <td>In GDB, type <br><code>
+ (gdb) monitor reset init<br>
+ (gdb) load<br>
+ (gdb) continue<br>
+ </code></td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+ cpsr: 0x000000d3 pc: 0x000000ec<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:71<br>
+ 71 DWORD a = 1;
+ </code>
+ </td>
+ <td><code>
+(gdb) monitor reset init<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+cleared protection for sectors 0 through 7 on flash bank 0<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+(gdb) load<br>
+Loading section .text, size 0x1a0 lma 0x4000000<br>
+Loading section .rodata, size 0x4 lma 0x40001a0<br>
+Start address 0x4000000, load size 420<br>
+Transfer rate: 25 KB/sec, 210 bytes/write.<br>
+(gdb) c<br>
+Continuing.<br>
+<br>
+Breakpoint 1, main () at src/main.c:69<br>
+69 DWORD a = 1;<br>
+(gdb)
+ </code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="DBG005"/>DBG005</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Hardware breakpoint</td>
+ <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
+ <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+ <code>
+ (gdb) monitor reset init<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+ (gdb) monitor gdb_breakpoint_override hard<br>
+ force hard breakpoints<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+ (gdb) continue<br>
+ </code>
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ </code>
+ </td>
+ <td>
+ <code>
+(gdb) monitor reset init<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+cleared protection for sectors 0 through 7 on flash bank 0<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+(gdb) load<br>
+Loading section .text, size 0x1a0 lma 0x0<br>
+Loading section .rodata, size 0x4 lma 0x1a0<br>
+Start address 0x0, load size 420<br>
+Transfer rate: 426 bytes/sec, 210 bytes/write.<br>
+(gdb) monitor gdb_breakpoint_override hard<br>
+force hard breakpoints<br>
+(gdb) break main<br>
+Breakpoint 1 at 0x144: file src/main.c, line 69.<br>
+(gdb) continue<br>
+Continuing.<br>
+Note: automatically using hardware breakpoints for read-only addresses.<br>
+<br>
+Breakpoint 1, main () at src/main.c:69<br>
+warning: Source file is more recent than executable.<br>
+69 DWORD a = 1;<br>
+Current language: auto<br>
+The current source language is "auto; currently c".<br>
+(gdb)
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="DBG006"/>DBG006</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Hardware breakpoint is set after a reset</td>
+ <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
+ <td>In GDB, type <br>
+ <code>
+ (gdb) monitor reset<br>
+ (gdb) monitor reg pc 0x100000<br>
+ pc (/32): 0x00100000<br>
+ (gdb) continue
+ </code><br>
+ where the value inserted in PC is the start address of the application
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ </code>
+ </td>
+ <td>
+ <code>
+(gdb) monitor reset init<br>
+RCLK - adaptive<br>
+SRST took 2ms to deassert<br>
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
+Trying to use configured scan chain anyway...<br>
+Bypassing JTAG setup events due to errors<br>
+SRST took 2ms to deassert<br>
+target state: halted<br>
+target halted in ARM state due to debug-request, current mode: Supervisor<br>
+cpsr: 0x000000d3 pc: 0x00000000<br>
+cleared protection for sectors 0 through 7 on flash bank 0<br>
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
+(gdb) c<br>
+Continuing.<br>
+<br>
+Breakpoint 1, main () at src/main.c:69<br>
+69 DWORD a = 1;<br>
+(gdb)
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="DBG007"/>DBG007</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Single step in ROM</td>
+ <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
+ <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+ <code>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+ (gdb) monitor arm7_9 force_hw_bkpts enable<br>
+ force hardware breakpoints enabled<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+ (gdb) continue<br>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ (gdb) step
+ </code>
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Supervisor<br>
+ cpsr: 0x60000013 pc: 0x0010013c<br>
+ 70 DWORD b = 2;<br>
+ </code>
+ </td>
+ <td><code>
+ (gdb) c<br>
+Continuing.<br>
+<br>
+Breakpoint 2, main () at src/main.c:69<br>
+69 DWORD a = 1;<br>
+Current language: auto<br>
+The current source language is "auto; currently c".<br>
+(gdb) step<br>
+70 DWORD b = 2;<br>
+(gdb)
+ </code></td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+<H2>RAM access</H2>
+Note: these tests are not designed to test/debug the target, but to test functionalities!
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="RAM001"/>RAM001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>32 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mww ram_address 0xdeadbeef 16<br>
+ > mdw ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
+ <code>
+ > mww 0x0 0xdeadbeef 16<br>
+ > mdw 0x0 32<br>
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
+ 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
+ </code>
+ </td>
+ <td><code>
+> mww 0x4000000 0xdeadbeef 16<br>
+> mdw 0x4000000 32 <br>
+0x04000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+0x04000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+0x04000040: e580100c e3a01802 e5801010 e3a01018 e5801018 e59f00a8 e59f10a8 e5801000<br>
+0x04000060: e3a00806 ee2f0f11 e321f0d7 e59fd098 e321f0db e59fd094 e321f0d3 e59fd090<br>
+>
+</code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RAM002"/>RAM002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>16 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mwh ram_address 0xbeef 16<br>
+ > mdh ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
+ <code>
+ > mwh 0x0 0xbeef 16<br>
+ > mdh 0x0 32<br>
+ 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
+ 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
+ >
+ </code>
+ </td>
+ <td><code>
+> mwh 0x4000000 0xbeef 16<br>
+> mdh 0x4000000 32<br>
+0x04000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
+0x04000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
+>
+ </code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="RAM003"/>RAM003</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>8 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mwb ram_address 0xab 16<br>
+ > mdb ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
+ <code>
+ > mwb ram_address 0xab 16<br>
+ > mdb ram_address 32<br>
+ 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
+ >
+ </code>
+ </td>
+ <td><code>
+> mwb 0x4000000 0xab 16<br>
+> mdb 0x4000000 32<br>
+0x04000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be<br>
+>
+ </code></td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+
+
+<H2>Flash access</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Actual output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="FLA001"/>FLA001</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Flash probe</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface:<br>
+ <code> > flash probe 0</code>
+ </td>
+ <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
+ <code>flash 'ecosflash' found at 0x01000000</code>
+ </td>
+ <td>
+ <code>
+ > flash probe 0<br>
+ flash 'str9x' found at 0x00000000<br>
+ >
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="FLA002"/>FLA002</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>flash fillw</td>
+ <td>Reset init is working, flash is probed</td>
+ <td>On the telnet interface<br>
+ <code> > flash fillw 0x1000000 0xdeadbeef 16
+ </code>
+ </td>
+ <td>The commands should execute without error. The output looks like:<br>
+ <code>
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+ </code><br>
+ To verify the contents of the flash:<br>
+ <code>
+ > mdw 0x1000000 32<br>
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ </code>
+ </td>
+ <td><code>
+> flash fillw 0x0 0xdeadbeef 16 <br>
+wrote 64 bytes to 0x00000000 in 0.020000s (3.125 kb/s)<br>
+> mdw 0 32<br>
+0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+>
+ </code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="FLA003"/>FLA003</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Flash erase</td>
+ <td>Reset init is working, flash is probed</td>
+ <td>On the telnet interface<br>
+ <code> > flash erase_address 0x1000000 0x20000
+ </code>
+ </td>
+ <td>The commands should execute without error.<br>
+ <code>
+ erased address 0x01000000 length 131072 in 4.970000s<br>
+ </code>
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
+ <code>
+ > mdw 0x1000000 32<br>
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ </code>
+ </td>
+ <td><code>
+> flash erase_address 0 0x20000<br>
+erased address 0x00000000 (length 131072) in 1.970000s (64.975 kb/s)<br>
+> mdw 0 32<br>
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+>
+</code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="FLA004"/>FLA004</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Entire flash erase</td>
+ <td>Reset init is working, flash is probed</td>
+ <td>On the telnet interface<br>
+ <code> > flash erase_address 0x0 0x80000
+ </code>
+ </td>
+ <td>The commands should execute without error.<br>
+ <code>
+ erased address 0x01000000 length 8192 in 4.970000s<br>
+ </code>
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
+ <code>
+ > mdw 0x1000000 32<br>
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ </code>
+ </td>
+ <td><code>
+> flash erase_address 0 0x80000<br>
+ erased address 0x00000000 length 524288 in 1.020000s<br>
+<br>
+> mdw 0 32<br>
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+</code></td>
+ <td>PASS</td>
+ </tr>
+ <tr>
+ <td><a name="FLA005"/>FLA005</td>
+ <td>STR912</td>
+ <td>ZY1000</td>
+ <td>Loading to flash from GDB</td>
+ <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
+ <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
+ <code>
+ (gdb) target remote ip:port<br>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+ </code>
+ </td>
+ <td>The output should look like:<br>
+ <code>
+ verified 404 bytes in 5.060000s
+ </code><br>
+ The failure message is something like:<br>
+ <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
+ </td>
+ <td>
+ <code>
+(gdb) load<br>
+Loading section .text, size 0x1a0 lma 0x0<br>
+Loading section .rodata, size 0x4 lma 0x1a0<br>
+Start address 0x0, load size 420<br>
+Transfer rate: 425 bytes/sec, 210 bytes/write.<br>
+(gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
+verified 420 bytes in 0.350000s (1.172 kb/s)<br>
+(gdb)
+ </code>
+ </td>
+ <td>PASS</td>
+ </tr>
+</table>
+
+</body>
+</html> \ No newline at end of file
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-22 21:54:39 +0000