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* XScale: clean up full_context() (#1)David Brownell2009-11-291-17/+32
| | | | | | | | | When fetching all the registers, XScale was doing various stupid things like calling number_to_mode() a few dozen times instead of just once, and mapping access to each register three times (again, instead of just once). Stop that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: debug entry uses new register mappingDavid Brownell2009-11-291-9/+10
| | | | | | | | Use the new mapping interfaces in the debug entry path. SPSR and the banked registers now have smaller and faster accessors ... use them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: initial PXA3xx supportMarek Vasut2009-11-291-11/+32
| | | | | | [dbrownell@users.sourceforge.net: user's guide; variant param is optional] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: uplevel add_{break,watch}point() error checksDavid Brownell2009-11-281-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | In target_type.h it's documented that the target must be halted for add_breakpoint() ... and with slight ambiguity, also for its add_watchpoint() sibling. So rather than verifying that constraint in the CPU drivers, do it in the target_add_{break,watch}point() routines. Add minor paranoia on the remove_*point() paths too: save the return value, and print it out in in the LOG_DEBUG message in case it's nonzero. Note that with some current cores, like all ARMv7 ones I've looked at, there's no technical issue preventing watchpoint or breakpoint add/remove operations on active cores. This model seems deeply wired into OpenOCD though. ALSO: the ARM targets were fairly "good" about enforcing that constraint themselves. The MIPS ones were relied on other code to catch such stuff, but it's not clear such code existed ... keep an eye out for new issues on MIPS. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: add stub {read,write}_phys routinesDavid Brownell2009-11-261-0/+20
| | | | | | | | | Just make these fail, instead of letting them write over potentially random memory. Users should be able to work around the lack of real implementations by disbling the MMU by hand ... until someone provides a Real Fix. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use ARRAY_SIZE macroZachary T Welch2009-11-251-2/+2
| | | | | Search and destroy lingering cases where the ARRAY_SIZE macro should be used to convey more intrinsic meaning in the OpenOCD code.
* remove target_type register_command callbackZachary T Welch2009-11-241-9/+4
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* xscale: use register_commands()Zachary T Welch2009-11-241-23/+107
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-14/+14
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-10/+10
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-221-6/+0
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-4/+1
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-10/+16
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-5/+6
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-4/+3
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use COMMAND_PARSE_ENABLE macro where appropriateZachary T Welch2009-11-181-38/+23
| | | | | | | | Updates all command parsing of simple "enable" and "disable" arguments. A few case in the tree use a tri-state or extended arguments, which cannot use this simple macro. Simlifies the xscale icache/dcache command handler logic.
* ARM: add is_arm_mode()David Brownell2009-11-171-4/+1
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-2/+3
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-46/+46
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-25/+25
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-19/+19
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-7/+6
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove some more duplicate includesDavid Brownell2009-11-171-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: fewere exit() callsDavid Brownell2009-11-161-4/+4
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fileio: improve API typesZachary T Welch2009-11-161-1/+1
| | | | | | | | | | | | | Use size_t instead of uint32_t when specifying file sizes. Update all consumers up through the layers to use size_t when required. These changes should be safe, but the higher-levels will need to be updated further to receive the intended benefits (i.e. large file support). Add error checking for fileio_read and file_write. Previously, all errors were being silently ignored, so this change might cause some problems for some people in some cases. However, it gives us the chance to handle any errors that do occur at higher-levels, rather than burying our heads in the sand.
* target: no implicit #includes of "register.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-2/+3
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove unused "bitfield" infrastructureDavid Brownell2009-11-131-2/+0
| | | | | | | | | | | | | | We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-4/+4
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-72/+72
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-12/+12
| | | | Remove misleading typedef and redundant suffix from struct reg.
* target_type_t -> struct target_typeZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct target_type.
* image_t -> struct imageZachary T Welch2009-11-131-1/+1
| | | | | | | Remove misleading typedef and redundant suffix from struct image. Also removes the typedef from enum image_type, as it is used in image.h only.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and just use struct arm.
* breakpoint_t -> struct breakpointZachary T Welch2009-11-131-11/+11
| | | | Remove misleading typedef and redundant suffix from struct breakpoint.
* xscale_trace_entry_t -> struct xscale_trace_entryZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct xscale_trace_entry.
* arm_instruction_t -> struct arm_instructionZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct arm_instruction.
* xscale_reg_t -> struct xscale_regZachary T Welch2009-11-131-6/+6
| | | | Remove misleading typedef and redundant suffix from struct xscale_reg.
* xscale_common_t -> struct xscale_commonZachary T Welch2009-11-131-52/+52
| | | | Remove misleading typedef and redundant suffix from struct xscale_common.
* xscale_trace_data_t -> struct xscale_trace_dataZachary T Welch2009-11-131-6/+6
| | | | Remove misleading typedef and redundant suffix from struct xscale_trace_data.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* watchpoint_t -> struct watchpointZachary T Welch2009-11-131-6/+6
| | | | Remove misleading typedef and redundant suffix from struct watchpoint.
* scan_field_t -> struct scan_fieldZachary T Welch2009-11-131-8/+8
| | | | Remove useless structure typedef.
* jtag_tap_t -> struct jtag_tapZachary T Welch2009-11-131-2/+2
| | | | | Search and destroy the jtag_tap_t typedef. This also cleans up a layering violation, removing the declaration from types.h.
* fileio_t -> struct fileioZachary T Welch2009-11-131-1/+1
| | | | Remove useless structure typedef.
* add CMD_NAME macro for command handlersZachary T Welch2009-11-131-7/+7
| | | | | By introducing the CMD_NAME macro, this parameter may be integrated as args[-1] in command.[ch], without touching any other call sites.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-30/+12
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* XScale uses the new inheritance/nesting schemeDavid Brownell2009-11-051-187/+118
| | | | | | | Use target_to_xscale(), replacing needless pointer traversals and simplifying a bunch of code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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