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* change #include "arm7tdmi.h" to <target/arm7tdmi.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "arm7tdmi.h" the following form should be used. #include <target/arm7tdmi.h> The exception is from .c files in the same directory.
* change #include "arm7_9_common.h" to <target/arm7_9_common.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "arm7_9_common.h" the following form should be used. #include <target/arm7_9_common.h> The exception is from .c files in the same directory.
* change #include "arm11.h" to <target/arm11.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "arm11.h" the following form should be used. #include <target/arm11.h> The exception is from .c files in the same directory.
* change #include "jtag.h" to <jtag/jtag.h>Zachary T Welch2009-12-035-5/+5
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "jtag.h" the following form should be used. #include <jtag/jtag.h> The exception is from .c files in the same directory.
* change #include "types.h" to <helper/types.h>Zachary T Welch2009-12-039-9/+9
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "types.h" the following form should be used. #include <helper/types.h> The exception is from .c files in the same directory.
* change #include "time_support.h" to <helper/time_support.h>Zachary T Welch2009-12-039-9/+9
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
* change #include "replacements.h" to <helper/replacements.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "replacements.h" the following form should be used. #include <helper/replacements.h> The exception is from .c files in the same directory.
* change #include "log.h" to <helper/log.h>Zachary T Welch2009-12-0310-10/+10
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "log.h" the following form should be used. #include <helper/log.h> The exception is from .c files in the same directory.
* change #include "jim.h" to <helper/jim.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "jim.h" the following form should be used. #include <helper/jim.h> The exception is from .c files in the same directory.
* change #include "fileio.h" to <helper/fileio.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "fileio.h" the following form should be used. #include <helper/fileio.h> The exception is from .c files in the same directory.
* change #include "command.h" to <helper/command.h>Zachary T Welch2009-12-032-2/+2
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "command.h" the following form should be used. #include <helper/command.h> The exception is from .c files in the same directory.
* change #include "binarybuffer.h" to <helper/binarybuffer.h>Zachary T Welch2009-12-035-5/+5
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "binarybuffer.h" the following form should be used. #include <helper/binarybuffer.h> The exception is from .c files in the same directory.
* allow #include directives to use module nameZachary T Welch2009-12-031-0/+1
| | | | | | | | | | | | Includes the src directory in the search path, so header files may be migrated from: #include "foo.h" to #include <module/foo.h> which is more conducive for installation.
* feroceon.c should be part of ARM7_9_SRCNicolas Pitre2009-12-031-2/+2
| | | | | | | The Feroceon and Dragonite cores are similar to the ARM926 and ARM966 cores respectively. Signed-off-by: Nicolas Pitre <nico@marvell.com>
* ARM11: don't expose DSCRDavid Brownell2009-12-022-185/+7
| | | | | | | | | | | Remove the remaining extra copy of DSCR, and the register cache of which it was a part. That cache wasn't a very safe, or even necessary, idea; it was essentialy letting debugger-private state be manipulated by Tcl code that couldn't know how to do it right. This makes the "reg" output of an ARM11 resemble what most other ARM cores produce ... forward motion in the "make ARM11 work like the rest of the ARM cores" Jihad!
* ARM11: store a clean copy of DSCRDavid Brownell2009-12-024-76/+56
| | | | | | | Just store a clean copy of DSCR in the per-CPU struct, so we trivially pass a pointer to a recent copy. This replaces the previous "last_dscr" and cleans up most of the related calling conventions ... but it doesn't remove the other DSCR copy.
* ARM11: don't expose WDTRDavid Brownell2009-12-022-14/+11
| | | | | | | | | Don't expose the WDTR register through the register cache any more. If anyone wants Tcl scripts to be able to use DCC based communication with app code in the target, this wouldn't do it. Bugfix: don't trust the Tcl-accessible version of DSCR to flag whether WDTR needs to be restored when resuming.
* ARM11: don't expose RDTRDavid Brownell2009-12-022-15/+11
| | | | | | | | | Don't expose the RDTR register through the register cache any more. If anyone wants Tcl scripts to be able to use DCC based communication with app code in the target, this wouldn't do it. Bugfix: don't trust the Tcl-accessible version of DSCR to flag whether RDTR needs to be restored when resuming.
* ARM11: streamline debug entryDavid Brownell2009-12-021-25/+20
| | | | | | | | | | | | | Streamline arm11_on_enter_debug_state() entry: - It should handle the standard updates: * target->debug_reason * target->state - Don't waste time re-reading DSCR; just pass it in Also rename the routine to "arm11_debug_entry()", matching the convention used elsewhere in OpenOCD.
* ARM11: remove arm11->targetDavid Brownell2009-12-023-20/+12
| | | | | Don't need/want arm11->target; we have arm11->arm.target instead. Also remove some unused watchpoint stuff.
* ARM DPM: tweak initializationDavid Brownell2009-12-026-23/+33
| | | | | | Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
* adding files required for distributionZachary T Welch2009-12-021-0/+1
| | | | | Add headers missing from Makefile rules to pass 'make distcheck'. These were included in the tree but were not added with those commits.
* fix 'target init' command registrationZachary T Welch2009-12-021-6/+6
| | | | | The command handler registration was put at the top level, rather than as a subcommand. Move it to where it belongs.
* target: factor init to 'target init'Zachary T Welch2009-12-021-0/+23
| | | | Adds 'target init' command handler, called as part of 'init'.
* target: factor target_init() into piecesZachary T Welch2009-12-021-69/+84
| | | | | Moves body of target initialization loop into a helper function, cleaning up its visual flow in the process.
* ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell2009-12-025-44/+33
| | | | | | | | | | | Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: label SP and LR correctlyDavid Brownell2009-12-021-12/+12
| | | | | | | | | | | Except for USR/SYS mode, the labels for the shadowed SP and LR registers were reversed. LR is r14; SP is r13. Fix. This would not affect GDB users; GDB references are positional. Only folk working directly with OpenOCD register values would have noticed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: basic watchpoint supportDavid Brownell2009-12-011-0/+66
| | | | | | | Actually this should handle both breakpoints and watchpoints ... but the DPM framework only handles watchpoints for now. Works on Beagle. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: core DPM support for watchpointsDavid Brownell2009-12-014-41/+302
| | | | | | | | | | | | | | | | | | | | | This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7a: move constants out of Cortex-A8 headerDavid Brownell2009-12-012-35/+48
| | | | | | These are architecturally defined, not core-specific. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove previous mcr()/mrc() methodsDavid Brownell2009-12-011-75/+0
| | | | | | We don't need this code, now that the DPM code handles it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: remove previous mcr()/mrc() methodsDavid Brownell2009-12-012-104/+1
| | | | | | | | We don't need this code, now that the DPM code handles it. Neither do we need the ARMv7-A CP15 operations; remove their remnants too. And disable a mostly-needless diagnostic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: implement mrc()/mcr() as DPM opsDavid Brownell2009-12-011-0/+59
| | | | | | | | | | | | | Instead of having separate ARM11 and Cortex-A8 implementations of this code, have one shared implementation which just builds on the existing "run instruction via R0" support. This enables followup patches to remove that now-unused code from those two drivers. (Patches to move the "mrc" and "mcr" code into "struct arm" are due too ... MIPS and other cores do not support those ARM-specific concepts.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-019-218/+228
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: stop using CP15 opsDavid Brownell2009-12-011-5/+36
| | | | | | | | | | | The ARMv7-A code uses read_cp15() to access fault registers. Instead, use DPM operations directly, passing in the relevant MRC instructions. This eliminates per-operation overhead (though it'll be hard to observe, this is uncommon) and helps eliminate read_cp15(). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: stop using CP15 opsDavid Brownell2009-12-011-16/+53
| | | | | | | | | | | | | | | | | | | | | There were two chunks of Cortex-A8 code which called the ARMv7-A CP15 operations; get rid of them, helping prepare to remove those methods completely: - post_debug_entry() can use the mrc() method to read its two registers. - write_memory() can use dpm->instr_write_data_r0() to flush the ICache and DCache ... doing it this way is actually faster since it reduces per-write overhead. Note that the mrc() method parameters are re-ordered with respect to the ARM instruction documentation, so that part can be confusing. Cleaned up the layout and comments in those areas a bit. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: restore_context() cleanupDavid Brownell2009-11-301-38/+30
| | | | | | | | | | | Clean up two aspects to this routine: bad naming, since it doesn't restore the context, just the banked registers; and excess indentation for the bulk of the code. Also make some of its call sites stash the function's return code; someday they should use it for error checking. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: context restore, cleanup/bugfixDavid Brownell2009-11-301-15/+29
| | | | | | | | | | | | | | This "loop over all registers" routine shared the same mess as full_context() in terms of dozens of needless number_to_mode() calls. Fix that, and comments, with related cleanup. The misnamed xscale_restore_context() had a related bug. It was restoring the *WRONG REGISTERS* ... always from whatever the current mode was, instead of using the copy from whichever register bank it was trying to restore. (But it marked the intended register as having been restored...) Fixed that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* do not extern 'interp' from command.cZachary T Welch2009-11-302-5/+7
| | | | | Adds 'interp' field to command_context, chasing the few remaining references to the global variable outside of the command module.
* target: avoid using interp global variableZachary T Welch2009-11-302-9/+11
| | | | | Adds 'interp' to target_event_action structure to avoid using the global variable of the same name.
* XScale: clean up full_context() (#2)David Brownell2009-11-291-39/+30
| | | | | | | Streamline the loop by continuing as soon as we know there's no work to be done; this lets us un-indent almost everything. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: clean up full_context() (#1)David Brownell2009-11-291-17/+32
| | | | | | | | | When fetching all the registers, XScale was doing various stupid things like calling number_to_mode() a few dozen times instead of just once, and mapping access to each register three times (again, instead of just once). Stop that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: debug entry uses new register mappingDavid Brownell2009-11-291-9/+10
| | | | | | | | Use the new mapping interfaces in the debug entry path. SPSR and the banked registers now have smaller and faster accessors ... use them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: initial PXA3xx supportMarek Vasut2009-11-292-11/+39
| | | | | | [dbrownell@users.sourceforge.net: user's guide; variant param is optional] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: fix warning on cygwinDavid Brownell2009-11-291-9/+22
| | | | | | Previous version of JTAG_DEBUG() macro hid this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: don't chain "struct arm" commandsDavid Brownell2009-11-281-3/+0
| | | | | | | | | | | | Those commands presume support for the "classic" set of CPU modes (FIQ, supervisor, IRQ, etc) ... which aren't supported by the ARMv7-M or ARMv6-M architectures. They also presume a "struct arm" base type, which this code doesn't use. We haven't cleaned up the register handling enough to be able to share any of those "base" methods. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add more stub handlers to testee targetZachary T Welch2009-11-281-2/+22
| | | | Prevent everything from crashing when exercising various commands.
* explode tcl_target_func into many handlersZachary T Welch2009-11-281-387/+521
| | | | | | | | Eliminate the monolithic tcl_target_func by registering each of its commands using the new chained command registration mechanism. Also chains the target's commands under the CPU command, though these may not work properly without some further modification.
* split jim_target into multiple handlersZachary T Welch2009-11-281-109/+137
| | | | | | | | The 'target' command group was implemented using its own command dispatching, which can be eliminated by using the new chained command registration mechanism. This patch splits the jim_target() function into individual handlers, which makes them to be visible to the help and usage commands. These one-trick handlers are much easier to understand.
* ARM11: fix warning on amd64David Brownell2009-11-281-1/+4
| | | | | | Previous version of JTAG_DEBUG() macro hid this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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