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* target files shouldn't #include <target/...h>David Brownell2009-12-1325-39/+38
| | | | | | | | | | | Make these ".h" files adopt the same policy the ".c" files already follow: don't use <subsystem/...h> syntax for private interfaces. If we ever get reviewed/supported "public" interfaces they should come exclusively from some include/... directory; that'll be the time to switch to <...> syntax for any subsystem's own interfaces. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: further shrink Jim-awarenessDavid Brownell2009-12-134-7/+10
| | | | | | | | | | | | | Don't include <helper/jim.h> from target.h ... not everything which touches targets needs to be able to talk to Jim. Plus, most files include this header by another path. Also, switch the affected files to use the classic sequence for #included files: all <framework/headers.h> first, then the "local_headers.h". This helps prevent growth of problematic layering, by minimizing entanglement. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: avoid pointless status returnsDavid Brownell2009-12-112-16/+11
| | | | | | | | For some routines that only returned ERROR_OK and where the caller never checked ... don't bother. Remove some noise, and bugfix some comments. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: support updating HW breakpointsDavid Brownell2009-12-112-52/+75
| | | | | | | | | | | Abstract the DPM breakpoint and watchpoint data structures to have a shared core for housekeeping. Abstract the code updating the watchpoint registers so that it can be used to update breakpoint registers. Then do so, when something has set up the breakpoint state used by this code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassembly fixes for LDC/STC/MRRC/MCRRDavid Brownell2009-12-111-18/+33
| | | | | | | Properly detect all of these, including the "2" variants; and bugfix parameter display for LDC and STC. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: minor cleanup, mostly ITR commentsDavid Brownell2009-12-112-28/+43
| | | | | | | | | | | | | ITR register handling seemed to be giving me problems, so I updated the comments to better say what the code is trying to do ... and to note the preconditions (one of which seems to be an issue) as listed in the ARM1136 TRM. Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code; all the callers already specify an exit path, since this register isn't usable with such vague semantics. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* optimisation: tiny optimisation for embedded iceØyvind Harboe2009-12-111-6/+5
| | | | | | | use two shift operations instead of three to set embedded ice register. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded hosts: optimize common code path for core arm operationsØyvind Harboe2009-12-112-46/+66
| | | | | | | avoid fn call for the if check on whether anything needs to be done. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: update arm_opcodes.h copyrightDavid Brownell2009-12-091-0/+3
| | | | | | | I neglected to copy Magnus' copyright when I moved several declarations from the ARMv7-M header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Comment and doxygen fixesDavid Brownell2009-12-092-4/+14
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ETM: only include oocd_trace.h when tracing enabled.Spencer Oliver2009-12-091-0/+3
| | | | | | Fixes build issue on systems that do not have <termios.h>, eg native win32. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* target: remove more exit() callsDavid Brownell2009-12-082-9/+2
| | | | | | | | These were all basically "can't happen" cases ... like having state be corrupted by an alpha particle after the previous check for whether a value was in-range. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove needless "extern"sDavid Brownell2009-12-084-24/+8
| | | | | | | | | | Most of these happened to be in the target.h file. Some of those are associated with symbols that could be removed at some point ... e.g. NVP_ASSERT/true and its sibling NVP_DEASSERT/false. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: move 'extern' decls to *.h filesDavid Brownell2009-12-085-15/+15
| | | | | | | | The exception being declarations for drivers. Those should be split out in some clean way -- like driver add/remove calls made by initialization code -- but that's for another day. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: cygwin complile fixesDavid Brownell2009-12-081-4/+6
| | | | | | | It's as if despite integers being 32-bits, GCC refuses to convert a "uint32_t" to one of them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* build: add build/src to include pathØyvind Harboe2009-12-081-1/+2
| | | | | | This allows including generated include files. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: cope with stupidheaded compilerDavid Brownell2009-12-071-2/+1
| | | | | | | | Some versions of GCC don't understand that if you mask with 0x3 then have cases 0-3, it's not possible for a variable assigned in all those branches to have no value at end-of-case. Feh. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: list number of HW breakpoints/watchpointsDavid Brownell2009-12-073-0/+12
| | | | | | | | | | | | | | | When starting up, say how many hardware breakpoints and watchpoints are available on various targets. This makes it easier to tell GDB how many of those resources exist. Its remote protocol currently has no way to ask OpenOCD for that information, so it must configured by hand (or not at all). Update the docs to mention this; remove obsolete "don't do this" info. Presentation of GDB setup information is still a mess, but at least it calls out the three components that need setup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add debug_reason_name()David Brownell2009-12-075-8/+19
| | | | | | | | Provide and use debug_reason_name() instead of expecting targets to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and the code becomes more clear too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: don't clone arm_arch_state() codeDavid Brownell2009-12-074-33/+8
| | | | | | | | | | | Have various ARM cores delegate to arm_arch_state() to display basic information, instead of duplicating that logic. This shrinks the code, makes them all report when semihosting is active, and highlights which data are specific to this core. (Like ARM720 not having separate instruction and data caches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: use <target/arm.h> not armv4_5.hDavid Brownell2009-12-0718-194/+225
| | | | | | | | | | | | | | Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-0715-32/+34
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-0717-247/+276
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell2009-12-073-20/+32
| | | | | | | | | | | | Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassemble two more v6+ instructionsDavid Brownell2009-12-071-12/+71
| | | | | | | | | | | The SRS and RFE instructions speed exception entry/exit by making it easy to save and restore PC and SPSR. This handles both ARM and Thumb2 encodings. Fix minor PLD goofage; that "should never reach this point" can't happen, so remove it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: don't write low bits of watchpoint valueDavid Brownell2009-12-071-1/+1
| | | | | | | The low two bits are defined as should-be-zero-or-presereved. We'll take the zero option, it's easier to enforce. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: use breakpoint on ARM7Nicolas Pitre2009-12-041-7/+9
| | | | | | | | | | | | Fall back to software breakpoint when vector catch isn't available. Possible enhancements: - add extra optional command parameter to select high vectors - add extra optional command parameter to select hardware breakpoint Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: work with both low and high vectorsNicolas Pitre2009-12-041-6/+4
| | | | | Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: doc updates for main headerDavid Brownell2009-12-041-3/+11
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell2009-12-046-11/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell2009-12-043-17/+17
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: misc generic cleanupDavid Brownell2009-12-044-13/+28
| | | | | | | | | | | Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell2009-12-044-9/+9
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: switch target_to_armv4_5() to target_to_arm()David Brownell2009-12-048-20/+18
| | | | | | And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_state_* as arm_state_*David Brownell2009-12-0412-23/+23
| | | | | | And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-048-39/+39
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-048-131/+131
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-0410-67/+67
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: report watchpoint trigger insnDavid Brownell2009-12-041-0/+18
| | | | | | | As with Cortex-A8, the WFAR register holds useful information that should be recorded and, where relevant, displayed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: basic watchpoint supportDavid Brownell2009-12-044-9/+100
| | | | | | Use the DPM watchpoint support; remove old incomplete stubs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: tweak TAP ops and debuggingDavid Brownell2009-12-042-23/+61
| | | | | | | | | | | | | | | | | | Tweak scanchain 7 debug messaging: - show register addresses in decimal, matching ARM docs; - remove some pointless noise Avoid some needless roundtrips: - skip SCAN_N when SCREG already holds that number (speeds up polling and other common operations) - avoid zeroing vcr twice on resume Show the IR opcode as a label ("RESTART") too; and in decimal, matching ARM docs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: semihosting entry cleanupDavid Brownell2009-12-041-8/+39
| | | | | | | | | Clean up arm_semihosting() entry a bit, comment some issues and just which SVC opcodes are getting intercepted. Microcontroller profile cores will need a new entry, since they use BKPT instead (and don't have either SVC mode or an SPSR register). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove semihosting globalsDavid Brownell2009-12-045-33/+48
| | | | | | | | Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: cygwin build fixesDavid Brownell2009-12-042-4/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* basic ARM semihosting supportNicolas Pitre2009-12-034-0/+516
| | | | | | | | | | | | | | | | | | | | Semihosting enables code running on an ARM target to use the I/O facilities on the host computer. The target application must be linked against a library that forwards operation requests by using the SVC instruction that is trapped at the Supervisor Call vector by the debugger. The "hosted" library version provided with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example. This is currently available for ARM9 processors, but any ARM variant should be able to support this with little additional work. Tested using binaries compiled with Sourcery G++ Lite 2009q1-161 and ARM RVCT 3.0. [dbrownell@users.sourceforge.net: doc tweaks, NEWS] Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* doxygen: remove some warningsDavid Brownell2009-12-031-0/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: tweak arch_state()David Brownell2009-12-031-10/+4
| | | | | | | | | Punt to the armv4_5_arch_state() for all the common stuff, to shrink code and so we will get any improvements it provides. Don't hide watchpoint status if we happen to be in "abort" mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-037-100/+60
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use shared DSCR bit namesDavid Brownell2009-12-033-42/+24
| | | | | | | | | | | | | For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: make DSCR bit defs sharableDavid Brownell2009-12-033-33/+43
| | | | | | | | | | | | | | | | Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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