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* scripts: update flash bank namesSpencer Oliver2010-05-136-12/+12
| | | | | | As the flash bank name is now unique update the scripts to suit. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* telo: update configuration scripts to matched master branchmichal smulski2010-04-243-64/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* TCL scripts: update to current "flash bank" syntaxAntonio Borneo2010-03-261-1/+1
| | | | | | | | | | | | | | While "flash bank" syntax has been changed long ago, several tcl script are still not fully update. Fix following cases related with "cfi" driver: - syntax error: the mandatory <name> parameter is missing - warning: the <target> parameter is a number, instead of the target name - the comment line above the command does not report actual syntax Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* PIC32: add Microchip Explorer16 cfgSpencer Oliver2010-03-161-4/+1
| | | | | | | - add Microchip Explorer16 cfg using PIC32MX360F512L PIM. - remove reset config from PIC32 target cfg. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* rename jtag_nsrst_assert_width as adapter_nsrst_assert_widthDavid Brownell2010-03-151-1/+1
| | | | | | | | | | | Globally rename "jtag_nsrst_assert_width" as "adapter_nsrst_assert_width", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename jtag_nsrst_delay as adapter_nsrst_delayDavid Brownell2010-03-1534-36/+36
| | | | | | | | | | | Globally rename "jtag_nsrst_delay" as "adapter_nsrst_delay", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename jtag_khz as adapter_khzDavid Brownell2010-03-1518-35/+35
| | | | | | | | | | | Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. (We may want to update it to include a nag message too.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32MX: update cfg scriptSpencer Oliver2010-03-151-10/+23
| | | | | | | | The default config script will now dynamically setup the BMX registers in the reset init script. This will also work if the user overrides the default working area. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* PIC32: add flash algorithm supportSpencer Oliver2010-03-101-4/+12
| | | | | | | | | | | | | Add flash algorithm support for the PIC32MX. Still a few things todo but this dramatically decreases the programing time, eg. approx programming for 2.5k test file. - without fastload: 60secs - with fastload: 45secs - with fastload and algorithm: 2secs. Add new devices to supported list. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* LPC1768 updates, IAR board supportDavid Brownell2010-03-021-25/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Add target/mc13224v.cfgMariano Alvira2010-02-271-0/+54
| | | | | | | | | | | | | | | | | The MC13224V is a FreeScale ARM7TDMI based IEEE802.15.4 platform for Zigbee and similar low-power wireless applications. Using PIP (Platform In Package) technology, it integrates: an RF balun and matching network; a buck converter (only an external inductor is necessary); 96KB of SRAM; and 128KB of non-volatile memory. It has an integrated bootloader and can boot from a variety of sources: external SPI or I2C non-volatile memory, an image loaded over UART1, or the internal non-volatile memory. The image loaded from one of these sources is executed directly from SRAM starting at location 0x00400000. Open source development code at http://mc1322x.devl.org Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC1768.cfg -- partial fixes for bogus reset-init handlerDavid Brownell2010-02-151-4/+4
| | | | | | | | | Cortex-M targets don't support ARM instructions. Leave the NVIC.VTOR setup alone, but comment how the whole routine looks like one big bug... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target library: configuration files for openocd tested with Atmel SAM-ICE V6 ↵Viktar Palstsiuk2010-02-111-0/+44
| | | | | | JTAG. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* str730.cfg: fix incorrect mem regionsSpencer Oliver2010-02-091-2/+2
| | | | | | - update str73x mem regions to correct values. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* scripts: Phytec/LPC2350 config scriptsEthan Eade2010-02-041-0/+36
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* AT91R40008/Ethernut 3 configurationHarald Kipp2010-02-021-32/+9
| | | | | | | | | | Moved board specific settings from target/at91r40008.cfg to a new file board/ethernut3.cfg. Set correct CPUTAPID. Reset delay increased, see MIC2775 data sheet. Increased work area size from 16k to 128k. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/str7x: Reset init unlocks the flashEdgar Grimberg2010-02-022-2/+17
| | | | | | | | | | | For STR7x flash, the device cannot be queried for the protect status. The solution is to remove the protection on reset init. The driver also initialises the sector protect field to unprotected. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* flash/str7x: After reset init the flash is unlockedEdgar Grimberg2010-02-021-1/+9
| | | | | | | | | | | | | | The default state of the STR7 flash after a reset init is unlocked. The information in the flash driver now reflects this. The information about the lock status cannot be read from the flash chip, so the user is informed that flash info might not contain accurate information. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/target/at91sam3u4e.cfg: changed case in dependent fileMichael Grzeschik2010-01-201-1/+1
| | | | | | | | openocd does not start with the target configfile due to the case in the dependent config file. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32: enable ram executionSpencer Oliver2010-01-051-1/+17
| | | | | | add reset-init script to allow ram execution from reset, this is required for ejtag fastdata access. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* target.cfg: update to use new flash configuration syntaxSpencer Oliver2009-12-1711-15/+15
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* more tcl/{board,target} cleanupDavid Brownell2009-12-155-7/+7
| | | | | | | | | | | | | | Remove more remnants of the old "jtag_device" syntax. Don't [format "%s.cpu" $_CHIPNAME] ... it's needless complexity. Remove various non-supported "-variant" target options; they're not needed often at all. Flag some of the board files as needing to have and use target files for the TAP and target declarations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* testing/examples/.../*cfg: rm jtag_device callsDavid Brownell2009-12-151-3/+0
| | | | | | | That syntax has been obsolete forever and is now gone; remove a few remaining references. Shows how seldom this stuff gets used. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add basic dsp563xx supportmkdorg@users.sourceforge.net2009-12-151-0/+38
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* imx31: move srst delay into config scriptØyvind Harboe2009-12-151-0/+2
| | | | | | reset init/run now works again. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* lm3748: use new Stellaris config fileDavid Brownell2009-12-141-29/+0
| | | | | | Use the new file, and remove the old target/lm3s3748.cfg one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Common target file for Stellaris chipsYegor Yefremov2009-12-141-0/+49
| | | | | | | | | Common target.cfg file for LM3S CPU family [dbrownell@users.sourceforge.net: rename, generalize more] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* OMAP2420: define reset-assert eventDavid Brownell2009-12-071-0/+7
| | | | | | | | | Behave like OMAP3530: force global software reset. Given the patch to teach ARM11 how to use these events, and use VCR to catch the reset vector, this works better than either the current reset logic or than using SRST. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Tcl and doc: update to match new 'arm mcr ...' etcDavid Brownell2009-12-012-5/+5
| | | | | | Make them match the C code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: at91eb40a.cfg is a board, not a target.Øyvind Harboe2009-12-011-62/+0
| | | | | | | Also updated to use target name when creating flash and set jtag_khz to 16000. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* create target/pxa3xx.cfgMarek Vasut2009-11-291-0/+86
| | | | | | [dbrownell@users.sourceforge.net; remove pxa255 comment] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* omap3530.cfg: use new "reset-assert" eventDavid Brownell2009-11-271-2/+2
| | | | | | Replaces previous "reset-assert-pre" workaround. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* omap3530.cfg: yes we have SRAM!David Brownell2009-11-251-0/+3
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: TAP id for Hilscher netX 500David Brownell2009-11-201-9/+7
| | | | | | Based on email from "Martin Kaul <martin.kaul@leuze.de>". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* update 'flash bank' usage in scriptsZachary T Welch2009-11-1939-45/+90
| | | | | Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-164-4/+4
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: ETM + ETB supportDavid Brownell2009-11-134-4/+15
| | | | | | | | | | | Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420, so update that configuration. (That's an ARM1136ejs, ETB, OpenGL ES1.1, C55x DSP, etc.) Also update the other ARM11 ETM + ETB targets in the tree to set up these modules. (Not tested.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX2* + ETB targets: hook up ETM and ETBDavid Brownell2009-11-132-1/+10
| | | | | | | ARM9 cores with an ETB will have a matching ETM. Hook them both up by default. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: label ETBs correctlyDavid Brownell2009-11-135-28/+26
| | | | | | | | | | | | | | | | | | Various cores with an ETB have its TAP misnamed ... either as a boundary scan TAP or as the iMX "Secure JTAG Controller" (which is, among other things, a JRC that could be used to shorten scan chains). Use the correct name for these TAPs, which we can recognize since their IDs were assigned by ARM and these chips all document the presence of an ETB. The 0x2b900f0f is ETB11; the 0x1b900f0f is an older module, just called "ETB". Also shrink the ETB's IR configuration; the default IR-Capture value is fine, and the mask can specify that all four bits are safe to check (per ARM documentation). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: (re)move some bogus reset_config linesDavid Brownell2009-11-104-13/+0
| | | | | | | General rule, this is all board-specific and doesn't belong in target config files. Some of these were just cosmetic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stm32.cfg: remove reset_configThomas Kindler2009-11-101-3/+0
| | | | | | | | | | | | | | | Here's a patch for the double-reset problem on STM32. I've tested downloading and debugging with GDB and Eclipse, and everything seems to work fine. This effectively sets reset_config to none. trst_only would also be ok, but that's better left to a board configuration file since not all boards wire it up. The NVIC is used to trigger reset, which at least on this chip also pulses nSRST so the whole system does get rest -- exactly once. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old mrc/mcr commandsØyvind Harboe2009-11-102-5/+5
| | | | | | Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* telo.cfg: fix search pathsØyvind Harboe2009-11-101-4/+4
| | | | | | | Add the missing "target/" prefix for scripts in the target folder. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target.cfg: remove "-work-area-virt 0"David Brownell2009-11-0835-35/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove "-ircapture 0x1 -irmask 0x1" from stm32.cfgFreddie Chopin2009-11-011-2/+5
| | | | | | | | Gets rid of the runtime warning "stm32.bs: nonstandard IR mask" [dbrownell@users.sourceforge.net: line lengths, note issue, section ref] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: use $_TARGETNAME for flashFreddie Chopin2009-10-3113-13/+13
| | | | | | | | | This gets rid of runtime warnings from the use of numbers. STM32 and LPC2103 were tested. Other LPC updates are the same, and so are safe. The CFI updates match other tested changes now in the tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: force reset configDavid Brownell2009-10-261-0/+4
| | | | | These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG.
* omap3530: target reset/init improvementsDavid Brownell2009-10-261-15/+25
| | | | | | | | | | | | | | | | | Now I can issue "reset halt" and have everything act smoothly; the vector_catch hardware is obviously not kicking in, but the rest of the reset sequence acts sanely. - TAP "setup" event enables the DAP, not omap3_dbginit (resolving a chicken/egg bug I noted a while back) - Remove stuff from omap3_dbginit which should never be used in event handlers - Cope better with slow clocking during reset Also, stop hard-wiring the target name: use the input params in the standard way, and set up $_TARGETNAME as an output param. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix syntax of mww phys.Øyvind Harboe2009-10-251-11/+11
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* mww_phys retired. Replaced by generic mww phys in target.cØyvind Harboe2009-10-211-11/+11
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