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authorTrygve Laugstøl <trygvis@inamo.no>2015-12-14 20:41:48 +0100
committerTrygve Laugstøl <trygvis@inamo.no>2015-12-14 20:41:48 +0100
commitd3e577db0bb3b3343ac58dad1c3e9ab06f051d0b (patch)
tree138bd34b4dfbfca9c525c169a275b1ac139638a0
parentc2aae4ccb63158f197c3d0629082e7699dfe8e25 (diff)
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o Adding debug output test.
-rw-r--r--.gitignore1
-rw-r--r--gdb-start7
-rw-r--r--test1.cpp21
3 files changed, 20 insertions, 9 deletions
diff --git a/.gitignore b/.gitignore
index 378eac2..08fe6ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
+.idea
build
diff --git a/gdb-start b/gdb-start
index e46fd1c..23195c0 100644
--- a/gdb-start
+++ b/gdb-start
@@ -21,9 +21,10 @@ monitor reset halt
monitor flash probe 0
monitor stm32f1x mass_erase 0
monitor stm32f1x.cpu mwb 0x20000000 0x5a 20480
-monitor flash write_bank 0 test1.elf.bin
-delete breakpoint
-hbreak main
+monitor flash write_bank 0 test1.elf.bin 0
+monitor arm semihosting enable
+# delete breakpoint
+# hbreak main
end
monitor reset halt
diff --git a/test1.cpp b/test1.cpp
index 85dee38..cd9f801 100644
--- a/test1.cpp
+++ b/test1.cpp
@@ -47,14 +47,23 @@ void HardFault_Handler_C(uint32_t * hardfault_args) {
} while (1);
}
-/*
- * Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL,
- * GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset
- * register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
- * (GPIOx_LCKR).
- */
+__attribute__((naked))
+void send_command(int command, void* message) {
+ __asm volatile (
+ "mov r0, %[cmd] \n\t"
+ "mov r1, %[msg] \n\t"
+ "bkpt #0xAB" : : [cmd] "r" (command), [msg] "r" (message) : "r0", "r1", "memory"
+ );
+}
int main() {
+ uint32_t message[] = {
+ 2,
+ (uint32_t)"Hello World!\r\n",
+ 14
+ };
+ send_command(0x05, &message);
+
SystemInit();
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTPENDED_Msk | SCB_SHCSR_BUSFAULTENA_Msk;