o Moving tinyprintf and stm libraries under thirdparty.

6 files changed, 4579 insertions, 0 deletions

diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c
new file mode 100644
index 0000000..2e0b76d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c
@@ -0,0 +1,1722 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_cec.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file provides all the STM32100E-EVAL HDMI-CEC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_cec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @defgroup STM32100E_EVAL_CEC
+  * @brief This file includes the CEC Stack driver for HDMI-CEC Module
+  *        of STM32100E-EVAL board.
+  * @{
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Defines
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Variables
+  * @{
+  */
+
+__IO uint32_t ReceivedFrame = 0;
+__IO uint32_t SendFrame = 0;
+__IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
+__IO uint8_t BufferPointer[15];
+__IO uint32_t ReceiveStatus = 0;
+__IO uint32_t SendStatus = 0;
+__IO uint8_t TransErrorCode = 0;
+__IO uint8_t RecepErrorCode = 0;
+__IO uint8_t MyLogicalAddress = 0;
+__IO uint16_t MyPhysicalAddress = 0;
+__IO uint8_t DeviceType = 0;
+#ifdef HDMI_CEC_USE_DDC
+__IO uint8_t pBuffer[256];
+__IO uint16_t NumByteToRead = 255;
+#endif
+__IO uint8_t CECDevicesNumber = 0;
+
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
+
+__IO uint8_t FeatureOpcode = 0;
+__IO uint8_t AbortReason = 0;
+__IO uint8_t DeviceCount = 0;
+
+HDMI_CEC_Map HDMI_CEC_MapStruct;
+HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
+
+/* CEC follower addresses */
+uint8_t* HDMI_CEC_Follower_String[13][2] =
+  {
+    {(uint8_t*)"         TV         ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 1  ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 2  ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 1         ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 1  ", (uint8_t*)"0"},
+    {(uint8_t*)"   Audio System     ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 2         ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 3         ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 2  ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 3  ", (uint8_t*)"0"},
+    {(uint8_t*)"      Tuner 4       ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 3  ", (uint8_t*)"0"},
+    {(uint8_t*)"     Broadcast      ", (uint8_t*)"1"}
+  };
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Function_Prototypes
+  * @{
+  */
+static HDMI_CEC_Error PhysicalAddressDiscovery(void);
+static HDMI_CEC_Error LogicalAddressAllocation(void);
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HDMI CEC.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  CEC_InitTypeDef CEC_InitStructure;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint8_t sendcount = 0;
+
+#ifdef HDMI_CEC_USE_DDC
+  I2C_InitTypeDef  I2C_InitStructure;
+  /* Enable CEC_I2C clocks */
+  RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
+
+  /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
+  RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE);
+#endif
+
+  /* Enable CEC clocks */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
+
+  /* Enable CEC_LINE_GPIO clocks */
+  RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
+
+  /* Configure CEC_LINE_GPIO as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
+
+#ifdef HDMI_CEC_USE_DDC
+  /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN;
+  GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
+
+/* This configuration is only when the HDMI CEC is configured as source.
+   The HDMI source has to provide the +5V Power signal to the sink. 
+   On STM32100E-EVAL borad, you have to solder the SB4 Solder bridge.
+   Then, the source will wait for HPD signal to be asserted from the sink.
+   Once the HPD signal is detected the source shall read the EDID structure 
+   throuhgh the DDC channel. */
+  /* Configure CEC_HPD_GPIO as Input pull down */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
+  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
+
+
+/* This configuration is only when the HDMI CEC is configured as sink.
+   The HDMI sink has to wait for the +5V Power signal from the source. 
+   On STM32100E-EVAL borad, SB4 Solder bridge should be open (default configuration).
+   Then, the sink will assert the HPD signal to inform the source that the EDID
+   is ready for read through DDC channel. In this implementation, the EDID structure
+   is not implemented. */
+/*  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
+
+  HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */
+  
+  /* Enable CEC_I2C */
+  I2C_Cmd(HDMI_CEC_I2C, ENABLE);
+
+  /* I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED;
+  I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
+#endif
+
+  /* Physical Address discovery */
+  errorstatus = PhysicalAddressDiscovery();
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device not connected (Physical Address lost) */
+    return(errorstatus);
+  }
+
+
+  /* CEC DeInit */
+  CEC_DeInit();
+
+  /* Configure CEC */
+  CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
+  CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
+  CEC_Init(&CEC_InitStructure);
+
+  /* Set Prescaler value for APB1 clock = 24MHz */
+  CEC_SetPrescaler(0x4AF);
+
+  /* Enable CEC */
+  CEC_Cmd(ENABLE);
+
+  /* Logical Address Allocation */
+  sendcount = 0;
+  errorstatus = LogicalAddressAllocation();
+
+  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+  {
+    sendcount++;
+    errorstatus = LogicalAddressAllocation();
+  }
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device Unregistred */
+    return(errorstatus);
+  }
+
+  HDMI_CEC_CheckConnectedDevices();
+  
+  /* Set the CEC initiator address */
+  CEC_OwnAddressConfig(MyLogicalAddress);
+
+  /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
+  CEC_ITConfig(ENABLE);
+
+  /* Report physical address*/
+  errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  sendcount = 0;
+
+  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+  {
+    sendcount++;
+    errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  }
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device Unregistred */
+    return(errorstatus);
+  }
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Transmit message by taking  data from typedef struct CEC_Meassage
+  * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
+  *         the message to be sent.
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  __IO uint32_t count = 0, j = 0;
+
+  SendFrame = 0;
+  SendStatus = 0;
+  TxCounter = 0;
+  BufferCount = 0;
+
+  HDMI_CEC_TX_MessageStructPrivate =  *HDMI_CEC_TX_MessageStructure;
+
+  /* Initialize BufferPointer */
+  for (j = 0; j < 15; j++)
+  {
+    BufferPointer[j] = 0;
+  }
+
+  BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
+
+  for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
+  {
+    BufferPointer[BufferCount] =  HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1];
+  }
+
+  CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+  /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
+  CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header);
+
+  /* Initiate Message Transmission */
+  CEC_StartOfMessage();
+
+  while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (SendStatus == 0)
+  {
+    errorstatus = (HDMI_CEC_Error) TransErrorCode;
+  }
+
+  return errorstatus;
+}
+
+
+/**
+  * @brief  Get the ESR register status.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+
+  /* Bit timing error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BIT_TIMING;
+  }
+  /* Bit period error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BIT_PERIOD;
+  }
+  /* Recieve error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_BLOCK_FINISHED;
+  }
+  /* Start bit error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET)
+  {
+    errorstatus = HDMI_CEC_START_BIT;
+  }
+  /* Acknowledge error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE;
+  }
+  /* Line error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET)
+  {
+    errorstatus = HDMI_CEC_LINE;
+  }
+  /* Transfert error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET)
+  {
+    errorstatus = HDMI_CEC_TX_BLOCK_FINISHED;
+  }
+  /* Clear All errors */
+  CEC_ClearFlag(CEC_FLAG_RERR);
+  CEC_ClearFlag(CEC_FLAG_TERR);
+  return errorstatus;
+}
+
+/**
+  * @brief  Allows to process all the interrupts that are high.
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_ProcessIRQSrc(void)
+{
+  /********************** Reception *********************************************/
+  /* Check if a reception error occured */
+  if (CEC_GetFlagStatus(CEC_FLAG_RERR))
+  {
+    /* Set receive status bit (Error) */
+    ReceiveStatus  = 0;
+    ReceivedFrame  = 1;
+    RecepErrorCode = HDMI_CEC_GetErrorStatus();
+    CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
+  }
+  else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
+  {
+    /* Check if the byte received is the last one of the message */
+    if (CEC_GetFlagStatus(CEC_FLAG_REOM))
+    {
+      HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
+      HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter;
+      ReceiveStatus = SUCCESS;
+      ReceivedFrame = 1;
+    }
+    /* Check if the byte received is a Header */
+    else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
+    {
+      ReceiveStatus = 0;
+      HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte();
+      RxCounter = 0;
+    }
+    /* Receive each byte except header in the reception buffer */
+    else
+    {
+      if (RxCounter != 0)
+      {
+        HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
+        RxCounter++;
+      }
+      else
+      {
+        HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte();
+        RxCounter++;
+      }
+      
+    }
+    /* Clear all reception flags */
+    CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
+  }
+
+  /********************** Transmission ******************************************/
+  /* Check if a transmission error occured */
+  if (CEC_GetFlagStatus(CEC_FLAG_TERR))
+  {
+    TransErrorCode = HDMI_CEC_GetErrorStatus();
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    SendFrame = 1;
+    SendStatus = 0;
+  }
+  /* Check if end of message bit is set in the data to be transmitted */
+  else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
+  {
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
+    CEC_EndOfMessageCmd(DISABLE);
+    SendFrame = 1;
+    SendStatus = SUCCESS;
+  }
+  /* Check if data byte has been sent */
+  else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
+  {
+    /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */
+    if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
+    {
+      CEC_SendDataByte(BufferPointer[TxCounter]);
+      TxCounter++;
+      CEC_ClearFlag(CEC_FLAG_TBTRF);
+      CEC_EndOfMessageCmd(ENABLE);
+    }
+    else
+    {
+      /* Put the byte in the TX Buffer */
+      CEC_SendDataByte(BufferPointer[TxCounter]);
+      TxCounter++;
+      CEC_ClearFlag(CEC_FLAG_TBTRF);
+    }
+  }
+}
+
+/**
+  * @brief  Report physical address to all other devices thus allowing any
+            device to create a map of the network.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  HDMI_CEC_Message HDMI_CEC_TX_Message;
+
+  HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
+  HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
+  HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
+  HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
+  HDMI_CEC_TX_Message.Operande[2] = DeviceType;
+  HDMI_CEC_TX_Message.TxMessageLength = 0x03;
+
+  errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
+
+  return  errorstatus;
+}
+
+/**
+  * @brief  Handle CEC command receive callback.
+  *         When receiving the STANDBY Opcode commande, the system is entred in
+  *         Stop mode and when wakeup, the PLL is configured as system clock and
+  *         the HSI is selected as PLL source.      
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_CommandCallBack(void)
+{
+  uint8_t i = 0, sendcount = 0;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  EXTI_InitTypeDef EXTI_InitStructure;
+
+  switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
+  {
+    case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
+      HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
+      HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
+      HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+      HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+      HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
+      HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t*)"1";
+      DeviceCount++;
+      break;
+
+    case HDMI_CEC_OPCODE_STANDBY:
+      /* CEC Line */
+      GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8);
+      /* Configure the CEC Line as EXTI Line on Falling Edge */
+      EXTI_ClearITPendingBit(EXTI_Line8);
+      EXTI_InitStructure.EXTI_Line = EXTI_Line8;
+      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+      EXTI_Init(&EXTI_InitStructure);
+      /* Request to enter Stop mode */
+      PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
+
+      /* Disable the CEC EXTI Line */
+      EXTI_InitStructure.EXTI_LineCmd = DISABLE;
+      EXTI_Init(&EXTI_InitStructure);
+      /* Configure the PLL Source */
+      RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
+
+      /* Enable PLL */ 
+      RCC_PLLCmd(ENABLE);
+
+      /* Wait till PLL is ready */
+      while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+      {
+      }
+
+      /* Select PLL as system clock source */
+      RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+      /* Wait till PLL is used as system clock source */
+      while(RCC_GetSYSCLKSource() != 0x08)
+      {
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GET_CEC_VERSION:
+      /* Send the Used CEC version */
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
+      /* Send the Physical address */
+      errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_FEATURE_ABORT:
+      /* The device doesn't support the requested message type, or that it cannot
+      execute it at the present time. */
+      FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
+      AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
+      /* Send the OSD name = STM32100E CEC*/
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
+      /* STM32100E*/
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x45;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
+      /* CEC */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_ROUTING_CHANGE:
+      for (i = 0;i < 0x14;i++)
+      {
+        if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F))
+        {
+          HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+          HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+          HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
+        }
+      }
+      break;
+
+    default:
+      /* Send Abort feature*/
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+  }
+}
+
+/**
+  * @brief  Check the connected CEC devices.
+  * @param  None
+  * @retval HDMI_CEC_Error
+  */
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0, i = 1;
+ 
+  /*----------------------------- TV device  ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x0);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[0][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Recording device 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x1);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[1][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Recording device 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x2);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[2][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x3);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Playback device 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x4);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Audio system ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x5);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x6);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x7);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Playback device 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x8);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Recording device 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x9);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Tuner 4 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0xA);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Playback device 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0xB);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  CECDevicesNumber = i - 1;
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Physical address discovery.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error PhysicalAddressDiscovery(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+#ifdef HDMI_CEC_USE_DDC
+  uint32_t index = 0, i = 0;
+#endif
+
+  /*------------------------------ Physical address discovery -----------------*/
+  if (HDMI_CEC_ROOT == 0x1)
+  {
+    MyPhysicalAddress = 0x0000;
+    /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
+       of the +5V power signal and the HPD should be well configured.
+       Implement here the EDID Structure to be sent to the HDMI source.
+       For more details please refer to the HDMI specification. 
+       The EDID structure should be sent to the device source using the DDC Channel
+       and using the HPD signal. */
+  }
+  else
+  {
+  
+#ifdef HDMI_CEC_USE_DDC  
+    /* The HDMI-CEC here is configured as source or as a repeater. The configuration
+       of the +5V power signal and the HPD should be well configured.
+       The source should wait for HPD and then read the EDID structure. */
+    while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET)
+    {
+    }
+    /* Wait for 100 ms after HPD was received */
+    for(i = 0; i < 0x5FFFF; i++)
+    {
+    }
+
+    /* Return the physical address using the I2C  by reading the 2 bytes 24 and
+      25 form the EDID */
+    /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */
+    /*!< While the bus is busy */
+    while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY))
+    {
+    }
+  
+    /*!< Send START condition */
+    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
+  
+    /*!< Test on EV5 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+    {
+    }
+   
+    /*!< Send EEPROM address for write */
+    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter);
+ 
+
+    /*!< Test on EV6 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+    {
+    }
+
+    /*!< Send the EEPROM's internal address to read from: Only one byte address */
+    I2C_SendData(HDMI_CEC_I2C, 0x00);  
+
+    /*!< Test on EV8 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+    {
+    }
+  
+    /*!< Send STRAT condition a second time */  
+    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
+  
+    /*!< Test on EV5 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+    {
+    }
+  
+    /*!< Send EEPROM address for read */
+    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver);
+  
+    /*!< Test on EV6 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+    {
+    }
+
+    /* While there is data to be read */
+    while (NumByteToRead-- > 1)
+    {
+      while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
+      {
+      }
+      for(i = 0; i < 0xFFF; i++)
+      {
+      }
+      pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C);
+    }
+
+    /* Disable Acknowledgement */
+    I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE);
+
+    /* Send STOP Condition */
+    I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE);
+
+    while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED));
+    pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C);
+
+    /* Enable Acknowledgement to be ready for another reception */
+    I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE);
+    MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]);
+#else
+    MyPhysicalAddress = 0x1000;
+#endif
+  }
+
+  return errorstatus;
+}
+/**
+  * @brief  Allocate the logical address.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error LogicalAddressAllocation(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0;
+
+  /*------------------ Logical address allocation -----------------------------*/
+  /* Get the device type */
+  /* Device type = CEC_TV */
+  if (DeviceType == HDMI_CEC_TV)
+  {
+    if (HDMI_CEC_ROOT)
+    {
+      MyLogicalAddress = 0x00;
+    }
+    else
+    {
+      CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0xEE);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      /* Wait till the polling message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x0E;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        MyLogicalAddress = 0x0F;
+        errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_RECORDING */
+  if (DeviceType == HDMI_CEC_RECORDING)
+  {
+    CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x11);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x01;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x22);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x02;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0x99);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x09;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_TUNER */
+  if (DeviceType == HDMI_CEC_TUNER)
+  {
+    CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x33);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x03;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x66);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x06;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0x77);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x07;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          /* Clear CEC CSR register */
+          CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+          CEC_EndOfMessageCmd(DISABLE);
+
+          CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
+
+          CEC_EndOfMessageCmd(ENABLE);
+
+          CEC_SendDataByte(0xAA);
+
+          /* Start of message */
+          CEC_StartOfMessage();
+
+          count = 0;
+
+          /* Wait till the header message is sent */
+          while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+          {
+            count++;
+          }
+
+          if (count >= HDMI_CEC_TIMEOUT_VALUE)
+          {
+            errorstatus = HDMI_CEC_TIMEOUT;
+            return(errorstatus);
+          }
+          errorstatus = HDMI_CEC_GetErrorStatus();
+
+          if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+          {
+            MyLogicalAddress = 0x0A;
+            errorstatus = HDMI_CEC_OK;
+          }
+          else if (errorstatus == HDMI_CEC_OK)
+          {
+            MyLogicalAddress = 0x0F;
+            errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+          }
+        }
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_PLAYBACK */
+  if (DeviceType == HDMI_CEC_PLAYBACK)
+  {
+    CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x44);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x04;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x88);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x08;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0xBB);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x0B;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC Audio System */
+  if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
+  {
+    CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x55);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x05;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      MyLogicalAddress = 0x0F;
+      errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+    }
+
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  return errorstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
+
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h
new file mode 100644
index 0000000..a899acf
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h
@@ -0,0 +1,290 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_cec.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the stm32100e_eval_cec
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_CEC_H
+#define __STM32100E_EVAL_CEC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */  
+
+/** @defgroup STM32100E_EVAL_CEC
+  * @{
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Types
+  * @{
+  */
+typedef enum
+{
+  HDMI_CEC_BIT_TIMING              = (1), /*!< CEC Bit Timing Error */
+  HDMI_CEC_BIT_PERIOD              = (2), /*!< CEC Bit Period Error */
+  HDMI_CEC_RX_BLOCK_FINISHED       = (3), /*!< CEC Receive Block finished Error */
+  HDMI_CEC_START_BIT               = (4), /*!< CEC Start Bit Error */
+  HDMI_CEC_BLOCK_ACKNOWLEDGE       = (5), /*!< CEC Block Acknowledge Error */
+  HDMI_CEC_LINE                    = (6), /*!< CEC Line Error */
+  HDMI_CEC_TX_BLOCK_FINISHED       = (7), /*!< CEC Transmit Block Transfer finished Error */
+  HDMI_CEC_DEVICE_UNREGISTRED      = (8), /*!< CEC Device Unregistred */
+  HDMI_CEC_TIMEOUT                 = (9), /*!< CEC TimeOut */
+  HDMI_CEC_OK                      = (10)  /*!< CEC OK */
+}HDMI_CEC_Error;
+
+typedef struct
+{
+  __IO uint8_t PhysicalAddress_A;
+  __IO uint8_t PhysicalAddress_B;
+  __IO uint8_t PhysicalAddress_C;
+  __IO uint8_t PhysicalAddress_D;
+  __IO uint8_t LogicalAddress;
+  __IO uint8_t DeviceType;
+}HDMI_CEC_Map;
+
+
+#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
+#define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
+
+/**
+* @brief  CEC Init Structure definition
+*/
+typedef struct
+{
+  __IO uint8_t Header;
+  __IO uint8_t Opcode;
+  __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
+  __IO uint8_t TxMessageLength;
+  __IO uint8_t RxMessageLength;
+}HDMI_CEC_Message;
+
+/**
+* @}
+*/
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @brief CEC device types
+  */
+#define HDMI_CEC_TV                                         0x00
+#define HDMI_CEC_RECORDING                                  0x01
+#define HDMI_CEC_TUNER                                      0x03
+#define HDMI_CEC_PLAYBACK                                   0x04
+#define HDMI_CEC_AUDIOSYSTEM                                0x05
+
+
+/**
+  * @brief  HDMI CEC I2C Interface pins
+  */
+#define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_6
+#define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_7
+#define HDMI_CEC_I2C_GPIO_PORT                              GPIOB
+#define HDMI_CEC_I2C_GPIO_CLK                               RCC_APB2Periph_GPIOB
+#define HDMI_CEC_I2C                                        I2C1
+#define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C1
+
+/**
+  * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
+  */
+#define HDMI_CEC_HPD_PIN                                    GPIO_Pin_9
+#define HDMI_CEC_HPD_GPIO_PORT                              GPIOB
+#define HDMI_CEC_HPD_GPIO_CLK                               RCC_APB2Periph_GPIOB
+
+/**
+  * @brief  HDMI CEC Interface pin
+  */
+#define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
+#define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
+#define HDMI_CEC_LINE_GPIO_CLK                              RCC_APB2Periph_GPIOB
+
+#define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
+#define HDMI_CEC_I2C_CLOCK_SPEED                            100000
+
+/**
+  * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
+  *         If you want to configure the STM32100E-EVAL board as CEC Root (Sink)
+  *         change the following define to 0x1    
+  */
+#define HDMI_CEC_ROOT                                       0x00
+
+/**
+  * @brief  To select if the DDC Channel will be used for physical address discovery
+  *         or not. To use the DDC Channel to read the EDID structure uncomment
+  *         the following line.   
+  *         If the device is configured as HMDI source it should read his own physical
+  *         address from the sink that is connected to.         
+  */
+/* #define HDMI_CEC_USE_DDC */                                    
+
+/**
+  * @brief  CEC version: V1.3a
+  */
+#define HDMI_CEC_VERSION                                    0x04
+
+/**
+  * @brief  Reason for Abort feature
+  */
+#define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
+#define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
+#define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
+#define HDMI_CEC_INVALID_OPERAND                            0x03
+#define HDMI_CEC_REFUSED                                    0x04
+
+/**
+  * @brief  HDMI CEC specific commands
+  */
+#define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
+#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
+#define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
+#define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
+#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
+#define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
+#define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
+#define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
+#define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
+#define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
+#define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
+#define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
+#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
+#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
+#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
+#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
+#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
+#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
+#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
+#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
+#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
+#define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
+#define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
+#define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
+#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
+#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
+#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
+#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
+#define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
+#define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
+#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
+#define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
+#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
+#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
+#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
+#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
+#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
+#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
+#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
+#define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
+#define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
+#define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
+#define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
+#define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
+#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
+#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
+#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
+#define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
+#define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
+#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
+#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
+#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
+#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
+#define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Macros
+  * @{
+  */
+/* HDMI_CEC_HPD: HDMI HPD pin low  */
+#define HDMI_CEC_HPD_LOW()       GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
+/* HDMI_CEC_HPD: HDMI HPD pin high  */
+#define HDMI_CEC_HPD_HIGH()      GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Functions
+  * @{
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void);
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
+void HDMI_CEC_ProcessIRQSrc(void);
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
+void HDMI_CEC_CommandCallBack(void);
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32100E_EVAL_CEC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c
new file mode 100644
index 0000000..735827b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c
@@ -0,0 +1,482 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_fsmc_onenand.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file provides a set of functions needed to drive the
+  *          KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_fsmc_onenand.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32100E_EVAL_FSMC_ONENAND
+  * @brief      This file provides a set of functions needed to drive the
+  *             KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
+  * @{
+  */ 
+#define BANK1_ONENAND1_ADDR           ((uint32_t)0x60000000)
+#define ONENAND_BOOTPARTITION_ADDR    ((uint32_t)BANK1_ONENAND1_ADDR)
+
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
+  * @{
+  */
+#define OneNAND_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
+  
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the OneNAND memory.
+  *         This function must be called before any write/read operation on the 
+  *         OneNAND.
+  * @param  None
+  * @retval None
+  */
+void OneNAND_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); 
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /* OneNAND Data lines configuration */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /*!< OneNAND Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+  
+  /*!< OneNAND Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | 
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+     
+  /*!< CLK, NOE and NWE configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  
+  /*!< NE1 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /*!< NL configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+  GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
+
+  /*!< NWAIT configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+    
+  /*-- FSMC Configuration ----------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0x01;
+  p.FSMC_AddressHoldTime = 0x00;
+  p.FSMC_DataSetupTime = 0x05;
+  p.FSMC_BusTurnAroundDuration = 0x02;
+  p.FSMC_CLKDivision = 0x1;
+  p.FSMC_DataLatency = 0x01;
+  p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;	
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); 
+}
+
+/**
+  * @brief  Resets the OneNAND memory.
+  * @param  None
+  * @retval None
+  */
+void OneNAND_Reset(void)
+{
+  OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
+}
+
+/**
+  * @brief  Reads OneNAND memory's Manufacturer and Device Code.
+  * @param  OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
+  *         the Manufacturer and Device Code.  
+  * @retval None
+  */
+void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
+{
+  uint16_t status = 0x0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  /* Read ID data */
+  OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
+  OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
+
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
+}
+
+/**
+  * @brief  Unlocks the specified OneNAND memory block (128Kb).
+  * @param  BlockNumber: specifies the block number to be erased. This parameter
+  *         should be between 0 and 511.
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
+{
+  uint16_t  status = 0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Erases the specified OneNAND memory block (128Kb).
+  * @param  BlockNumber: specifies the block number to be erased. This parameter
+  *         should be between 0 and 511.
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
+{
+  uint16_t status = 0x0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+
+  /* Erase operation */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
+
+  /* Wait till no error is generated */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x0400) == 0x0400)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Writes a Half-word buffer to the OneNAND memory. 
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: OneNAND memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of half-words to write. 
+  * @retval OneNAND memory Controller Status.
+  */
+uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
+{
+  uint32_t datacounter = 0;
+  uint16_t status = 0;
+
+  /* Load the buffer to be written into the DATA RAM0*/ 
+  for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
+  {
+    *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
+  } 
+
+  /* Write operation from DATA RAM0 to NAND address*/ 
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);  /* NAND Flash start page address */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */ 
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Wait till the write interrupt is set */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x40) != 0x40)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Reads a block of data from the OneNAND memory using asynchronous mode.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         OneNAND memory.
+  * @param  ReadAddr: OneNAND memory internal address to read from.
+  * @param  NumHalfwordToRead: number of half-words to read.
+  * @retval None
+  */
+void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
+{
+  uint16_t datatmp = 0x0, index = 0;
+  uint16_t status = 0;
+
+  datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); 
+
+  /* Set the asynchronous read mode */
+  OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
+
+  /* Load data from the read address to the DATA RAM 1 setor 1 */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Read Controller status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+
+  /* Read data */
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
+  {
+    /* Read a Halfword from the memory */
+    *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
+    index++;
+  } 
+}
+
+/**
+  * @brief  Reads a block of data from the OneNAND memory using synchronous mode.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         OneNAND memory.
+  * @param  ReadAddr: OneNAND memory internal address to read from.
+  * @param  NumHalfwordToRead: number of half-words to read.
+  * @retval None
+  */
+void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
+{
+  uint16_t index = 0;
+  uint16_t status = 0;
+
+  /* Set the asynchronous read mode */
+  OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
+  
+
+  /* Load data from the read address to the DATA RAM 1 setor 1 */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Read Controller status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+
+  /* Read data */
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
+  {
+   *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
+    index++;
+  }
+}
+
+/**
+  * @brief  Reads the OneNAND memory Interrupt status. 
+  * @param  None
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_ReadStatus(void)
+{
+  __IO uint16_t status = 0x0;
+
+  /* Read Status */
+  return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
+}
+
+/**
+  * @brief  Reads the OneNAND Controller status. 
+  * @param  None
+  * @retval OneNAND Controller Status.
+  */
+uint16_t OneNAND_ReadControllerStatus(void)
+{
+  __IO uint16_t status = 0x0;
+
+  /* Read Controller Status */
+  return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h
new file mode 100644
index 0000000..3e4340d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h
@@ -0,0 +1,189 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_fsmc_onenand.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32100e_eval_fsmc_onenand firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+   
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_FSMC_ONENAND_H
+#define __STM32100E_EVAL_FSMC_ONENAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32100E_EVAL_FSMC_ONENAND
+  * @{
+  */  
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Types
+  * @{
+  */
+typedef struct
+{
+  uint16_t Manufacturer_ID;
+  uint16_t Device_ID;
+}OneNAND_IDTypeDef;
+
+/* OneNand Status */
+typedef enum
+{
+  OneNAND_SUCCESS = 0,
+  OneNAND_ONGOING,
+  OneNAND_ERROR,
+  OneNAND_TIMEOUT
+}OneNAND_Status;
+
+typedef struct 
+{
+  uint16_t Block;
+  uint16_t Page;
+} OneNAND_ADDRESS; 
+/**
+  * @}
+  */
+  
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
+  * @{
+  */
+/** 
+  * @brief  OneNAND memory command  
+  */  
+#define OneNAND_CMD_ERASE                    ((uint16_t)0x0094)
+#define OneNAND_CMD_PROGRAM                  ((uint16_t)0x0080)
+#define OneNAND_CMD_RESET                    ((uint16_t)0x00F0)
+#define OneNAND_CMD_READ_ID                  ((uint16_t)0x0090)
+#define OneNAND_CMD_UNLOCK                   ((uint16_t)0x0023)
+#define OneNAND_CMD_LOAD                     ((uint16_t)0x0000)
+
+/** 
+  * @brief OneNand Register description  
+  */  
+#define OneNAND_REG_MANUFACTERID             ((uint32_t)0x1E000) /* Manufacturer identification */
+#define OneNAND_REG_DEVICEID                 ((uint32_t)0x1E002) /* Device identification */
+#define OneNAND_REG_DATABUFFERSIZE           ((uint32_t)0x1E006) /* Data Buffer size */
+#define OneNAND_REG_BOOTBUFFERSIZE           ((uint32_t)0x1E008) /* Boot Buffer size */
+#define OneNAND_REG_AMOUNTOFBUFFERS          ((uint32_t)0x1E00A) /* Amount of data/boot buffers */
+#define OneNAND_REG_TECHNOLOGY               ((uint32_t)0x1E00C) /* Info about technology */
+#define OneNAND_REG_STARTADDRESS1            ((uint32_t)0x1E200) /* Nand Flash Block Address */
+#define OneNAND_REG_STARTADDRESS3            ((uint32_t)0x1E204) /* Destination Block address for copy back program */
+#define OneNAND_REG_STARTADDRESS4            ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */
+#define OneNAND_REG_STARTADDRESINT8_T        ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */
+#define OneNAND_REG_STARTBUFFER              ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many
+                                                                     buffers to use for the data transfer */
+#define OneNAND_REG_COMMAND                  ((uint32_t)0x1E440) /* Host control and memory operation commands*/
+#define OneNAND_REG_SYSTEMCONFIGURATION      ((uint32_t)0x1E442) /* Memory and host interface configuration */
+#define OneNAND_REG_CONTROLSTATUS            ((uint32_t)0x1E480) /* Control status and result of memory operation */
+#define OneNAND_REG_INTERRUPT                ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */
+#define OneNAND_REG_STARTBLOCKADDRESS        ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */
+#define OneNAND_REG_WRITEPROTECTIONSTATUS    ((uint32_t)0x1E49C) /* Current memory Write Protection status */
+
+/** 
+  * @brief OneNand Memory partition description  
+  */
+#define OneNAND_DATA_RAM_0_0_ADD            ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */
+#define OneNAND_DATA_RAM_0_0_REG            ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_1_ADD            ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */
+#define OneNAND_DATA_RAM_0_1_REG            ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_2_ADD            ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */
+#define OneNAND_DATA_RAM_0_2_REG            ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_3_ADD            ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */
+#define OneNAND_DATA_RAM_0_3_REG            ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_0_ADD            ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */
+#define OneNAND_DATA_RAM_1_0_REG            ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_1_ADD            ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */
+#define OneNAND_DATA_RAM_1_1_REG            ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_2_ADD            ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */
+#define OneNAND_DATA_RAM_1_2_REG            ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_3_ADD            ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */
+#define OneNAND_DATA_RAM_1_3_REG            ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Functions
+  * @{
+  */ 
+void OneNAND_Init(void);
+void OneNAND_Reset(void);
+void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID);
+uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber);
+uint16_t OneNAND_EraseBlock(uint32_t BlockNumber);
+uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite);
+void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
+void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
+uint16_t OneNAND_ReadStatus(void);
+uint16_t OneNAND_ReadControllerStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32100E_EVAL_FSMC_ONENAND_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c
new file mode 100644
index 0000000..e45fc96
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c
@@ -0,0 +1,1405 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_ioe.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file includes the IO Expander driver for STMPE811 IO Expander 
+  *          devices.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+  
+    Note:
+    -----
+    - This driver uses the DMA method for sending and receiving data on I2C bus
+      which allow higher efficiency and reliability of the communication.
+    
+    SUPPORTED FEATURES:
+      - Touch Screen Features: Single point mode (Polling/Interrupt).     
+      - TempSensor Feature: accuracy not determined (Polling).
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt).
+      
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
+      - Joystick: config and Read (Polling/Interrupt)     
+  ----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_ioe.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+    
+/** @defgroup STM32100E_EVAL_IOE 
+  * @brief  This file includes the IO Expander driver for STMPE811 IO Expander 
+  *         devices.
+  * @{
+  */   
+
+/** @defgroup STM32100E_EVAL_IOE_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Defines
+  * @{
+  */ 
+#define TIMEOUT_MAX    0x1000 /*<! The value of the maximal timeout for I2C waiting loops */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Variables
+  * @{
+  */ 
+TS_STATE TS_State;              /*<! The global structure holding the TS state */
+
+uint32_t IOE_TimeOut = TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_FunctionPrototypes
+  * @{
+  */ 
+static uint16_t IOE_TS_Read_X(void);
+static uint16_t IOE_TS_Read_Y(void);
+static uint16_t IOE_TS_Read_Z(void);
+
+static void IOE_GPIO_Config(void);
+static void IOE_I2C_Config(void);
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer);
+static void IOE_EXTI_Config(void);
+
+#ifndef USE_Delay
+static void delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Functions
+  * @{
+  */ 
+
+
+/**
+  * @brief  Initializes and Configures the IO_Expanders Functionalities 
+  *         (Touch Screen ..) and configures all STM32100E-EVAL necessary
+  *         hardware (GPIOs, APB clocks ..).
+  * @param  None
+  * @retval IOE_OK if all initializations done correctly. Other value if error.
+  */
+uint8_t IOE_Config(void)
+{
+  /* Configure the needed pins */
+  IOE_GPIO_Config();
+  
+  /* Configure I2C peripheral */
+  IOE_I2C_Config();
+  
+  /* Read IO Expander 1 ID  */
+  if(IOE_IsOperational(IOE_1_ADDR))
+  {
+    return IOE1_NOT_OPERATIONAL;
+  } 
+  
+  /* Generate IOExpander Software reset */
+  IOE_Reset(IOE_1_ADDR); 
+  
+  /* ---------------------- IO Expander configuration --------------------- */
+  /* Enable the GPIO, Touch Screen and ADC functionalities */
+  IOE_FnctCmd(IOE_1_ADDR, IOE_TS_FCT | IOE_ADC_FCT | IOE_IO_FCT | IOE_TEMPSENS_FCT  , ENABLE);
+   
+  /* Touch Screen controller configuration */
+  IOE_TS_Config();
+  
+  /* Temperature Sensor configuration */
+  IOE_TempSens_Config();
+ 
+  /* ------------------------------------------------------------------------ */
+  
+  /* Configuration is OK */
+  return IOE_OK; 
+}
+
+/**
+  * @brief  Configures The selected interrupts on the IO Expanders.
+  * @param  IOE_ITSRC_Source: the source of the interrupts. Could be one or a 
+  *         combination of the following parameters:
+  *   @arg  IOE_ITSRC_TSC: Touch Screen interrupts.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source)
+{   
+  /* Configure the Interrupt output pin to generate low level (INT_CTRL) */
+  IOE_ITOutConfig(Polarity_Low, Type_Level);    
+  
+  /* Manage the Touch Screen Interrupts */  
+  if (IOE_ITSRC_Source & IOE_ITSRC_TSC)
+  {   
+    /* Enable the Global interrupt */  
+    IOE_GITCmd(IOE_1_ADDR, ENABLE);     
+           
+    /* Enable the Global GPIO Interrupt */
+    IOE_GITConfig(IOE_1_ADDR, (uint8_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV), ENABLE);    
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA); 
+  }
+  
+  /* Configure the Interrupt line as EXTI source */
+  IOE_EXTI_Config();    
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Writes a bit value to an output IO pin.
+  * @param IO_Pin: The output pin to be set or reset. 
+  *                IO_Pin_x: Where x can be from 0 to 7. 
+  * @param BitVal: The value to be set. This parameter can be one of the
+  *        following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
+  * @retval IOE_OK or PARAM_ERROR
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
+{
+  uint8_t DeviceAddr = 0;
+  
+  /* Get the IO expander Address according to which pin is to be controlled */
+  if (IO_Pin & IO1_OUT_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+  else
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Apply the bit value to the selected pin */
+  if (BitVal == BitReset)
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_CLR_PIN, IO_Pin);
+  }
+  else
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_SET_PIN, IO_Pin);
+  }
+  
+  return IOE_OK;
+}
+
+
+/**
+  * @brief  Returns the status of the selected input IO pin.
+  * @param IO_Pin: The input pin to be read. 
+  *                IO_Pin_x: Where x can be from 0 to 7.
+  *   @arg  JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)  
+  * @retval None
+  */
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin)
+{
+  uint8_t DeviceAddr = 0;
+  uint8_t tmp = 0;  
+  if (IO_Pin & IO1_IN_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+   else 
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Get all the Pins status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_MP_STA);
+  if ((tmp & (uint8_t)IO_Pin) != 0)
+  {
+    return BitSet;
+  }  
+  else 
+  {
+    return BitReset;
+  }
+}
+
+
+/**
+  * @brief  Returns Status and positions of the Touch screen.
+  * @param  None
+  * @retval Pointer to TS_STATE structure holding Touch Screen information.
+  */
+TS_STATE* IOE_TS_GetState(void)
+{
+  uint32_t xDiff, yDiff , x , y;
+  static uint32_t _x = 0, _y = 0;
+  
+  /* Check if the Touch detect event happenned */
+  TS_State.TouchDetected = (I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL) & 0x80);
+  if(TS_State.TouchDetected) 
+  {
+    x = IOE_TS_Read_X();
+    y = IOE_TS_Read_Y();
+    xDiff = x > _x? (x - _x): (_x - x);
+    yDiff = y > _y? (y - _y): (_y - y);       
+    if (xDiff + yDiff > 5)
+    {
+      _x = x;
+      _y = y;       
+    }
+  }  
+  /* Update the X position */
+  TS_State.X = _x;
+    
+  /* Update the Y position */  
+  TS_State.Y = _y;
+  /* Update the Z Pression index */  
+  TS_State.Z = IOE_TS_Read_Z();  
+  
+  /* Clear the interrupt pending bit and enable the FIFO again */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* Return pointer to the updated structure */
+  return &TS_State; 
+}
+
+/**
+  * @brief  Returns the temperature row value (in 16 bit format).
+  * @param  None
+  * @retval The temperature row value.
+  */
+uint32_t IOE_TempSens_GetData(void)
+{  
+  static __IO uint32_t tmp = 0;  
+    
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x03);
+  
+  /* Enable the TEMPSENS module */
+  tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); 
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA + 1); 
+  
+  tmp = (uint32_t)((33 * tmp * 100) / 751);
+  tmp = (uint32_t)((tmp + 5) / 10);
+  
+  /* return the temprature row value */
+  return tmp;
+}
+
+/**
+  * @brief  Checks the selected Global interrupt source pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Global_IT: the Global interrupt source to be checked, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt      
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  __IO uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
+  
+  if ((tmp & (uint8_t)Global_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected Global interrupt pending bit(s)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Global_IT: the Global interrupt to be cleared, could be any combination
+  *         of the following values:   
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); 
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Checks the status of the selected IO interrupt pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.             
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
+  
+  if ((tmp & (uint8_t)IO_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected IO interrupt pending bit(s).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.              
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);  
+  
+  /* Clear the Edge detection pending bit*/
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_ED, IO_IT);
+
+  /* Clear the Rising edge pending bit */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, IO_IT);
+
+  /* Clear the Falling edge pending bit */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, IO_IT); 
+
+  return IOE_OK;
+  
+}
+/**
+  * @brief  Checks if the selected device is correctly configured and 
+  *         communicates correctly ont the I2C bus.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval IOE_OK if IOE is operational. Other value if failure.
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr)
+{
+  /* Return Error if the ID is not correct */
+  if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
+  {
+    /* Check if a Timeout occured */
+    if (IOE_TimeOut == 0)
+    {
+      return(IOE_TimeoutUserCallback());
+    }
+    else
+    {
+      return IOE_FAILURE; /* ID is not Correct */
+    }
+  } 
+  else 
+  {
+    return IOE_OK; /* ID is correct */
+  }
+}
+
+/**
+  * @brief  Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_Reset(uint8_t DeviceAddr)
+{
+  /* Power Down the IO_Expander */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
+
+  /* wait for a delay to insure registers erasing */
+  _delay_(2); 
+  
+  /* Power On the Codec after the power off => all registers are reinitialized*/
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Reads the selected device's ID.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval The Device ID (two bytes).
+  */
+uint16_t IOE_ReadID(uint8_t DeviceAddr)
+{
+  uint16_t tmp = 0;
+
+  /* Read device ID  */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
+  tmp = (uint32_t)(tmp << 8);
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
+  
+  /* Return the ID */
+  return (uint16_t)tmp;
+}
+
+/**
+  * @brief  Configures the selcted IO Expander functionalities.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Fct: the functions to be configured. could be any 
+  *         combination of the following values:
+  *   @arg  IOE_IO_FCT : IO function
+  *   @arg  IOE_TS_FCT : Touch Screen function
+  *   @arg  IOE_ADC_FCT : ADC function
+  *   @arg  IOE_TEMPSENS_FCT : Tempreature Sensor function
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the register value */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the Functionalities to be Enabled */    
+    tmp &= ~(uint8_t)Fct;
+  }
+  else
+  {
+    /* Set the Functionalities to be Disabled */    
+    tmp |= (uint8_t)Fct;  
+  }
+  
+  /* Set the register value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Configures the selected pin direction (to be an input or an output)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x: Where x can be from 0 to 7.   
+  * @param  Direction: could be Direction_IN or Direction_OUT.      
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
+{
+  uint8_t tmp = 0;   
+  
+  /* Get all the Pins direction */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
+  
+  if (Direction != Direction_IN)
+  {
+    tmp |= (uint8_t)IO_Pin;
+  }  
+  else 
+  {
+    tmp &= ~(uint8_t)IO_Pin;
+  }
+  
+  /* Write the register new value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;      
+}
+
+/**
+  * @brief  Enables or disables the Global interrupt.
+  * @param  DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR.
+  * @param  NewState: could be ENABLE or DISABLE.        
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Read the Interrupt Control register  */
+  I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the global interrupts to be Enabled */    
+    tmp |= (uint8_t)IOE_GIT_EN;
+  }
+  else
+  {
+    /* Set the global interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IOE_GIT_EN;
+  }  
+  
+  /* Write Back the Interrupt Control register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;     
+}
+
+/**
+  * @brief  Configures the selected source to generate or not a global interrupt
+  * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  * @param Global_IT: the interrupt source to be configured, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts  
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current value of the INT_EN register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)Global_IT;  
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)Global_IT;
+  }
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures the selected pins to generate an interrupt or not.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: The IO interrupt to be configured. This parameter could be any
+  *         combination of the following values:
+  *   @arg  IO_IT_x: where x can be from 0 to 7.
+  * @param  NewState: could be ENABLE or DISABLE.  
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+ 
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)IO_IT;
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IO_IT;
+  }
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;   
+}
+
+/**
+  * @brief  Configures the touch Screen Controller (Single point detection)
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TS_Config(void)
+{
+  uint8_t tmp = 0;  
+  
+  /* Enable TSC Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); 
+  
+  /* Enable the TSC gloabl interrupts */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
+  tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); 
+  
+  /* Select Sample Time, bit number and ADC Reference */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
+  
+  /* Wait for ~20 ms */
+  _delay_(2);  
+  
+  /* Select the ADC clock speed: 3.25 MHz */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
+  
+  /* Select TSC pins in non default mode */  
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
+  tmp &= ~(uint8_t)TOUCH_IO_ALL;
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); 
+  
+  /* Select 2 nF filter capacitor */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);   
+  
+  /* Select single point reading  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
+  
+  /* Write 0x01 to clear the FIFO memory content. */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  
+  /* Write 0x00 to put the FIFO back into operation mode  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* set the data format for Z value: 7 fractional part and 1 whole part */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
+  
+  /* set the driving capability of the device for TSC pins: 50mA */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
+  
+  /* Use no tracking index, touchscreen controller operation mode (XYZ) and 
+     enable the TSC */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
+  
+  /*  Clear all the status pending bits */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); 
+  
+  /* Initialize the TS structure to their default values */ 
+  TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
+  
+  /* All configuration done */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures and enables the Temperature sensor module.
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TempSens_Config(void)
+{
+  __IO uint8_t tmp = 0;
+  
+  /* Enable Temperature Sensor Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);  
+  
+  /* Enable the TEMPSENS module */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x01);
+  
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x3);
+  
+  /* All configuration done */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the selected pin to be in Alternate function or not
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  NewState: State of the AF for the selected pin, could be 
+  *         ENABLE or DISABLE.       
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current state of the GPIO_AF register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected pins alternate function */
+    tmp |= (uint8_t)IO_Pin;
+  }
+  else
+  {
+    /* Disable the selected pins alternate function */   
+    tmp &= ~(uint8_t)IO_Pin;   
+  }
+  
+  /* Write back the new valu in GPIO_AF register */  
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);  
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Edge for which a transition is detectable for the
+  *         the selected pin.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  Edge: The edge which will be detected. This parameter can be one or a
+  *         a combination of follwing values: EDGE_FALLING and EDGE_RISING .
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
+{
+  uint8_t tmp1 = 0, tmp2 = 0;   
+  
+  /* Get the registers values */
+  tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
+  tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
+
+  /* Disable the Falling Edge */
+  tmp1 &= ~(uint8_t)IO_Pin;
+  /* Disable the Falling Edge */
+  tmp2 &= ~(uint8_t)IO_Pin;
+
+  /* Enable the Falling edge if selected */
+  if (Edge & EDGE_FALLING)
+  {
+    tmp1 |= (uint8_t)IO_Pin;
+  }
+
+  /* Enable the Rising edge if selected */
+  if (Edge & EDGE_RISING)
+  {
+    tmp2 |= (uint8_t)IO_Pin;
+  }
+
+  /* Write back the registers values */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
+  
+  /* if OK return 0 */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Interrupt line active state and format (level/edge)
+  * @param  Polarity: could be
+  *   @arg  Polarity_Low: Interrupt line is active Low/Falling edge      
+  *   @arg  Polarity_High: Interrupt line is active High/Rising edge      
+  * @param  Type: Interrupt line activity type, could be one of the following values
+  *   @arg  Type_Level: Interrupt line is active in level model         
+  *   @arg  Type_Edge: Interrupt line is active in edge model           
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
+{
+  uint8_t tmp = 0;
+  
+  /*  Get the register IOE_REG_INT_CTRL value */ 
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
+  
+  /* Mask the polarity and type bits */
+  tmp &= ~(uint8_t)0x06;
+    
+  /* Modify the Interrupt Output line configuration */
+  tmp |= (uint8_t)(Polarity | Type);
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
+    
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Writes a value in a register of the device through I2C.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. 
+  * @param  RegisterAddr: The target register adress
+  * @param  RegisterValue: The target register value to be written 
+  * @retval IOE_OK: if all operations are OK. Other value if error.
+  */
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t read_verif = 0;  
+  uint8_t IOE_BufferTX = 0;
+  
+  /* Get Value to be written */
+  IOE_BufferTX = RegisterValue;
+  
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX));
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+   
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(IOE_I2C, RegisterAddr);
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_TX_TCFLAG);
+  
+#ifdef VERIFY_WRITTENDATA
+  /* Verify (if needed) that the loaded data is correct  */
+  
+  /* Read the just written register*/
+  read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
+  /* Load the register and verify its value  */
+  if (read_verif != RegisterValue)
+  {
+    /* Control data wrongly tranfered */
+    read_verif = IOE_FAILURE;
+  }
+  else
+  {
+    /* Control data correctly transfered */
+    read_verif = 0;
+  }
+#endif
+  
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return read_verif;
+}
+
+/**
+  * @brief  Reads a register of the device through I2C.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval The value of the read register (0xAA if Timout occured)   
+  */
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
+{
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+    
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+    
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* return a pointer to the IOE_Buffer */
+  return (uint8_t)IOE_BufferRX[0];  
+}
+
+
+/**
+  * @brief  Reads a buffer of 2 bytes from the device registers.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval A pointer to the buffer containing the two returned bytes (in halfword).  
+  */
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
+{  
+  uint8_t tmp= 0;
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+   
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* Reorganize received data */  
+  tmp = IOE_BufferRX[0];
+  IOE_BufferRX[0] = IOE_BufferRX[1];
+  IOE_BufferRX[1] = tmp;
+  
+  /* return a pointer to the IOE_Buffer */
+  return *(uint16_t *)IOE_BufferRX;  
+}
+
+/**
+  * @brief  Return Touch Screen X position value
+  * @param  None
+  * @retval X position.
+  */
+static uint16_t IOE_TS_Read_X(void)
+{
+  int32_t x, xr;
+ 
+  x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
+  
+  /* first correction */
+  xr =  (x * 320) >> 12;
+  /* second correction */
+  xr = ((xr * 32)/29) - 17;
+  
+  if(xr <= 0)
+    xr = 0;
+  
+  return (uint16_t)(xr); 
+}
+
+/**
+  * @brief  Return Touch Screen Y position value
+  * @param  None
+  * @retval Y position.
+  */
+static uint16_t IOE_TS_Read_Y(void)
+{
+  int32_t y, yr;
+  y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
+  
+  yr= (y * 240) >> 12;
+  yr = ((yr * 240) / 217) - 12;
+  
+  if(yr <= 0)
+    yr = 0;
+  
+  return (uint16_t)(yr); 
+}
+
+/**
+  * @brief  Return Touch Screen Z position value
+  * @param  None
+  * @retval Z position.
+  */
+static uint16_t IOE_TS_Read_Z(void)
+{
+  uint32_t z;
+  z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
+  
+  
+  if(z <= 0)
+    z = 0;
+  
+  return (uint16_t)(z); 
+}
+
+/**
+  * @brief  Initializes the GPIO pins used by the IO expander.
+  * @param  None
+  * @retval None
+  */
+static void IOE_GPIO_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
+  RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE);
+  RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK
+                         | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Reset IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE);
+  
+  /* Release reset signal of IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE);
+  
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN;
+  GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Set EXTI pin as Input PullUp - IO_Expander_INT */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Connect IO Expander IT line to EXTI line */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
+}
+
+
+/**
+  * @brief  Configure the I2C Peripheral used to communicate with IO_Expanders.
+  * @param  None
+  * @retval None
+  */
+static void IOE_I2C_Config(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* IOE_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
+  
+  I2C_Init(IOE_I2C, &I2C_InitStructure);
+}
+
+
+/**
+  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
+  * @param  None
+  * @retval None
+  */
+
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+  
+  RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE);
+  
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
+   /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  
+  /* If using DMA for Reception */
+  if (Direction == IOE_DMA_RX)
+  {
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 2;
+    
+    DMA_DeInit(IOE_DMA_RX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure);
+  }
+   /* If using DMA for Transmission */
+  else if (Direction == IOE_DMA_TX)
+  { 
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 1;
+    
+    DMA_DeInit(IOE_DMA_TX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure);
+  }
+}
+
+/**
+  * @brief  Configures the IO expander Interrupt line and GPIO in EXTI mode.
+  * @param  None        
+  * @retval None
+  */
+static void IOE_EXTI_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+ 
+  /* Enable Button GPIO clock */
+  RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Configure Button pin as input floating */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Connect Button EXTI Line to Button GPIO Pin */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);  
+  
+  /* Configure Button EXTI line */
+  EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;  
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Enable and set Button EXTI Interrupt to the lowest priority */
+  NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = (100000 * nCount); index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+   
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h
new file mode 100644
index 0000000..76adb3b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h
@@ -0,0 +1,491 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_ioe.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the IO Expander
+  *   firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+    SUPPORTED FEATURES:
+      - Touch Screen Features: Single point mode (Polling/Interrupt).     
+      - TempSensor Feature: accuracy not determined (Polling).
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt).
+      
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
+      - Joystick: config and Read (Polling/Interrupt) 
+----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_IOE_H
+#define __STM32100E_EVAL_IOE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+    
+/** @defgroup STM32100E_EVAL_IOE 
+  * @{
+  */ 
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  Touch Screen Information structure  
+  */ 
+typedef struct
+{
+  uint16_t TouchDetected;
+  uint16_t X;
+  uint16_t Y;
+  uint16_t Z;
+}TS_STATE; 
+  
+
+/** 
+  * @brief  IO_Expander Error codes  
+  */ 
+typedef enum
+{
+  IOE_OK = 0,
+  IOE_FAILURE, 
+  IOE_TIMEOUT,
+  PARAM_ERROR,
+  IOE1_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/** 
+  * @brief  IO bit values  
+  */ 
+typedef enum
+{
+  BitReset = 0,
+  BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  IOE_DMA_TX = 0,
+  IOE_DMA_RX = 1
+}IOE_DMADirection_TypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ *        operation. The I2C_WriteDeviceRegister() function will then compare the
+ *        written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+/**
+ * @brief Uncomment the line below if you want to use user timeout callback.
+ *        Function prototypes is declared in this file but function body may be
+ *        implemented into user application.  
+ */
+/* #define USE_TIMEOUT_USER_CALLBACK */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif    
+
+/*------------------------------------------------------------------------------
+    Hardware Configuration 
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  I2C port definitions  
+  */
+#define IOE_I2C                          I2C2
+#define IOE_I2C_CLK                      RCC_APB1Periph_I2C2
+#define IOE_I2C_SCL_PIN                  GPIO_Pin_10
+#define IOE_I2C_SCL_GPIO_PORT            GPIOB
+#define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_SDA_PIN                  GPIO_Pin_11
+#define IOE_I2C_SDA_GPIO_PORT            GPIOB
+#define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_DR                       ((uint32_t)0x40005810)
+#define IOE_I2C_SPEED                    300000  
+
+/** 
+  * @brief  IOE DMA definitions  
+  */
+#define IOE_DMA                          DMA1
+#define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
+#define IOE_DMA_TX_CHANNEL               DMA1_Channel4
+#define IOE_DMA_RX_CHANNEL               DMA1_Channel5
+#define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC4
+#define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC5
+  
+
+/** 
+  * @brief  IO Expander Interrupt line on EXTI  
+  */ 
+#define IOE_IT_PIN                       GPIO_Pin_12
+#define IOE_IT_GPIO_PORT                 GPIOA
+#define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOA
+#define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOA
+#define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource12
+#define IOE_IT_EXTI_LINE                 EXTI_Line12
+#define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn       
+
+
+/** 
+  * @brief  The 7 bits IO Expanders adresses and chip IDs  
+  */ 
+#define IOE_1_ADDR                 0x82    
+#define STMPE811_ID                0x0811
+
+
+/*------------------------------------------------------------------------------
+    Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  IO Expander Functionalities definitions  
+  */ 
+#define IOE_ADC_FCT              0x01
+#define IOE_TS_FCT               0x02
+#define IOE_IO_FCT               0x04
+#define IOE_TEMPSENS_FCT         0x08
+
+/** 
+  * @brief  Interrupt source configuration definitons  
+  */ 
+#define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
+#define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 1 */
+
+/** 
+  * @brief  Glaobal Interrupts definitions  
+  */ 
+#define IOE_GIT_GPIO             0x80
+#define IOE_GIT_ADC              0x40
+#define IOE_GIT_TEMP             0x20
+#define IOE_GIT_FE               0x10
+#define IOE_GIT_FF               0x08
+#define IOE_GIT_FOV              0x04
+#define IOE_GIT_FTH              0x02
+#define IOE_GIT_TOUCH            0x01
+
+/**
+  * @brief IO Exapanders Pins definition 
+  */ 
+#define IO1_IN_ALL_PINS          (uint32_t)(IO_Pin_ALL)
+#define IO1_OUT_ALL_PINS         (uint32_t)(IO_Pin_ALL)
+
+
+/*------------------------------------------------------------------------------
+    STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  Identification registers  
+  */ 
+#define IOE_REG_CHP_ID             0x00
+#define IOE_REG_ID_VER             0x02
+
+/** 
+  * @brief  General Control Registers  
+  */ 
+#define IOE_REG_SYS_CTRL1          0x03
+#define IOE_REG_SYS_CTRL2          0x04
+#define IOE_REG_SPI_CFG            0x08 
+
+/** 
+  * @brief  Interrupt Control register  
+  */ 
+#define IOE_REG_INT_CTRL           0x09
+#define IOE_REG_INT_EN             0x0A
+#define IOE_REG_INT_STA            0x0B
+#define IOE_REG_GPIO_INT_EN        0x0C
+#define IOE_REG_GPIO_INT_STA       0x0D
+
+/** 
+  * @brief  GPIO Registers  
+  */ 
+#define IOE_REG_GPIO_SET_PIN       0x10
+#define IOE_REG_GPIO_CLR_PIN       0x11
+#define IOE_REG_GPIO_MP_STA        0x12
+#define IOE_REG_GPIO_DIR           0x13
+#define IOE_REG_GPIO_ED            0x14
+#define IOE_REG_GPIO_RE            0x15
+#define IOE_REG_GPIO_FE            0x16
+#define IOE_REG_GPIO_AF            0x17
+
+/** 
+  * @brief  ADC Registers  
+  */ 
+#define IOE_REG_ADC_INT_EN         0x0E
+#define IOE_REG_ADC_INT_STA        0x0F
+#define IOE_REG_ADC_CTRL1          0x20
+#define IOE_REG_ADC_CTRL2          0x21
+#define IOE_REG_ADC_CAPT           0x22
+#define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */ 
+
+/** 
+  * @brief  TouchScreen Registers  
+  */ 
+#define IOE_REG_TSC_CTRL           0x40
+#define IOE_REG_TSC_CFG            0x41
+#define IOE_REG_WDM_TR_X           0x42 
+#define IOE_REG_WDM_TR_Y           0x44
+#define IOE_REG_WDM_BL_X           0x46
+#define IOE_REG_WDM_BL_Y           0x48
+#define IOE_REG_FIFO_TH            0x4A
+#define IOE_REG_FIFO_STA           0x4B
+#define IOE_REG_FIFO_SIZE          0x4C
+#define IOE_REG_TSC_DATA_X         0x4D 
+#define IOE_REG_TSC_DATA_Y         0x4F
+#define IOE_REG_TSC_DATA_Z         0x51
+#define IOE_REG_TSC_DATA_XYZ       0x52 
+#define IOE_REG_TSC_FRACT_XYZ      0x56
+#define IOE_REG_TSC_DATA           0x57
+#define IOE_REG_TSC_I_DRIVE        0x58
+#define IOE_REG_TSC_SHIELD         0x59
+
+/** 
+  * @brief  Temperature Sensor registers  
+  */ 
+#define IOE_REG_TEMP_CTRL          0x60
+#define IOE_REG_TEMP_DATA          0x61
+#define IOE_REG_TEMP_TH            0x62
+
+/*------------------------------------------------------------------------------
+    Functions parameters defines
+------------------------------------------------------------------------------*/
+/**
+  * @brief Touch Screen Pins definition 
+  */ 
+#define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/** 
+  * @brief  IO Pins  
+  */ 
+#define IO_Pin_0                 0x01
+#define IO_Pin_1                 0x02
+#define IO_Pin_2                 0x04
+#define IO_Pin_3                 0x08
+#define IO_Pin_4                 0x10
+#define IO_Pin_5                 0x20
+#define IO_Pin_6                 0x40
+#define IO_Pin_7                 0x80
+#define IO_Pin_ALL               0xFF
+
+/** 
+  * @brief  IO Pin directions  
+  */ 
+#define Direction_IN             0x00
+#define Direction_OUT            0x01
+
+/** 
+  * @brief  Interrupt Line output parameters  
+  */ 
+#define Polarity_Low             0x00
+#define Polarity_High            0x04
+#define Type_Level               0x00
+#define Type_Edge                0x02
+
+/** 
+  * @brief IO Interrupts  
+  */ 
+#define IO_IT_0                  0x01
+#define IO_IT_1                  0x02
+#define IO_IT_2                  0x04
+#define IO_IT_3                  0x08
+#define IO_IT_4                  0x10
+#define IO_IT_5                  0x20
+#define IO_IT_6                  0x40
+#define IO_IT_7                  0x80
+#define ALL_IT                   0xFF
+#define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
+
+/** 
+  * @brief  Edge detection value  
+  */ 
+#define EDGE_FALLING              0x01
+#define EDGE_RISING               0x02
+
+/** 
+  * @brief  Global interrupt Enable bit  
+  */ 
+#define IOE_GIT_EN                0x01
+
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Functions
+  * @{
+  */ 
+
+/** 
+  * @brief  Configuration and initialization functions  
+  */
+uint8_t IOE_Config(void);
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t IOE_TimeoutUserCallback(void);
+#else
+ #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+
+/** 
+  * @brief IO pins control functions
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
+
+/** 
+  * @brief Touch Screen controller functions
+  */
+TS_STATE* IOE_TS_GetState(void);
+
+/** 
+  * @brief Interrupts Mangement functions
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+
+
+/** 
+  * @brief Temperature Sensor functions
+  */
+uint32_t IOE_TempSens_GetData(void);
+
+
+/** 
+  * @brief IO-Expander Control functions
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr);
+uint8_t IOE_Reset(uint8_t DeviceAddr);
+uint16_t IOE_ReadID(uint8_t DeviceAddr);
+
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
+
+/** 
+  * @brief Low Layer functions
+  */
+uint8_t IOE_TS_Config(void);
+uint8_t IOE_TempSens_Config(void);
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
+
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
+#ifdef __cplusplus
+}
+
+#endif
+#endif /* __STM32100E_EVAL_IOE_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */     
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/