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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html new file mode 100644 index 0000000..2d8c7d6 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html @@ -0,0 +1,207 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>CoreDebug_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" 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initNavTree('struct_core_debug___type.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">CoreDebug_Type Struct Reference</div> </div> +</div> +<div class="contents"> +<!-- doxytag: class="CoreDebug_Type" --> +<p>Structure type to access the Core Debug Register (CoreDebug). +</p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">DHCSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register. <a href="#a25c14c022c73a725a1736e903431095d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__O uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">DCRSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register. <a href="#afefa84bce7497652353a1b76d405d983"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">DCRDR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register. <a href="#ab8f4bb076402b61f7be6308075a789c9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">DEMCR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. <a href="#a5cdd51dbe3ebb7041880714430edd52d"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="ab8f4bb076402b61f7be6308075a789c9"></a><!-- doxytag: member="CoreDebug_Type::DCRDR" ref="ab8f4bb076402b61f7be6308075a789c9" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">CoreDebug_Type::DCRDR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="afefa84bce7497652353a1b76d405d983"></a><!-- doxytag: member="CoreDebug_Type::DCRSR" ref="afefa84bce7497652353a1b76d405d983" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O uint32_t <a class="el" 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