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Diffstat (limited to 'thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS')
135 files changed, 31151 insertions, 0 deletions
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font-family: Arial; color: blue;"><a href="../../../../../../Release_Notes.html">Back to Release page</a></span></td> + </tr> +<tr style=""> +<td style="padding: 1.5pt;"> +<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release +Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img style="border: 0px solid ; width: 86px; height: 65px;" src="../../../../../_htmresc/logo.bmp" id="_x0000_i1025" alt=""></span><span style="font-size: 10pt;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900"> +<tbody> +<tr> +<td style="padding: 0cm;" valign="top"> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2> +<ol style="margin-top: 0cm;" start="1" type="1"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS +update History</a><o:p></o:p></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li> +</ol> +<span style="font-family: "Times New Roman";"></span> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS +update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.1 / 09-March-2012<o:p></o:p></span></h3> + <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> + + <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.0 / 27-January-2012<o:p></o:p></span></h3> + <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> + + <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update directory structure to be compliant with CMSIS V2.1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the new license agreement</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for Cortex-M3 revision <span style="font-style: italic;">__CM3_REV</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Allow +modification of some constants by the application code, definition of +these constants is now bracketed by <span style="font-style: italic;">#if !defined</span><span style="font-style: italic;"></span>. The concerned constant are <span style="font-style: italic;">HSE_VALUE</span>, <span style="font-style: italic;">HSI_VALUE</span> and <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for <span style="font-style: italic;">DAC CR</span> register</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for <span style="font-style: italic;">FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4</span> registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Definition for </span><span style="font-size: 10pt; font-family: Verdana;">Flash keys moved from stm32f10x_flash.c to stm32f10x.h<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add startup file for <span style="font-style: italic;">TASKING</span> toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; text-decoration: underline; font-style: italic;">V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1)</span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline; font-style: italic;"> compatibility update</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Due to the </span><span style="font-size: 10pt; font-family: Verdana;"> directory structure </span><span style="font-size: 10pt; font-family: Verdana;">difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to </span><span style="font-size: 10pt; font-family: Verdana;">V3.6.0 </span><span style="font-size: 10pt; font-family: Verdana;">you need to perform the following update:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In +the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3 +CMSIS files are included by default in your development toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the compiler preprocessor, update path of </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> CMSIS</span> <span style="font-style: italic;">include</span> files from </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\CM3\DeviceSupport\ST\</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">to</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"> </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Include</span><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the project settings, update path of <span style="font-style: italic;">startup_stm32f10x_xx.s</span> file from</span><span style="font-size: 10pt; font-family: Verdana;"> Libraries\CMSIS\CM3\DeviceSupport\ST\</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\startup\”Compiler”</span> to </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\”Compiler”</span></li></ul></ul></ul><div style="margin-left: 40px;"><div style="margin-left: 80px;"><span style="font-size: 10pt; font-family: Verdana;">where, "Compiler" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO</span><br></div><span style="font-size: 10pt; font-family: Verdana;"></span></div> + <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3> + <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> + + <ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h +</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt +definition for STM32F10x High-density Value line devices.<br> +</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file provided within the CMSIS folder. <br> +</span></li> + + </ul> + + <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0 +- 10/15/2010</span></h3> + + <ol> +<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li> + </ol> + + <ul style="margin-top: 0in;" type="disc"> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support +for <b>STM32F10x High-density Value line devices</b>.</span></li> + </ul> + <ol start="2"> + <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li> + </ol> + + + + <ul style="margin-top: 0in;" type="disc"> +<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br> + </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li> +</ul> + <li class="MsoNormal" style=""> + + <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">All +STM32 devices definitions are commented by default. User has to select the +appropriate device before starting else an error will be signaled on compile +time.</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"<span style="font-weight: bold;">bool</span>" type removed.</span><br> + <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li> +</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br> + <span style="font-size: 10pt; font-family: Verdana;"></span></li> + <ul> +<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br> +<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">" +to select if the user want to place the Vector Table in internal SRAM. +An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br> + </span></li> + + </ul> +<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three +startup files for STM32 High-density Value line devices: + <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul> + </ul> + <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0 +- 04/16/2010</span></h3> + +<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol> +<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support +for <b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol> + + <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br> + </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for </span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br> + <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. </span><span style="font-size: 10pt; font-family: Verdana;"><br> + </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three +startup files for STM32 XL-density devices: + <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ Handler (was missing in previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0 +- 03/01/2010</span></h3> +<ol style="margin-top: 0in;" start="1" type="1"> +<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li> +</ol> +<ul style="margin-top: 0in;" type="disc"> + + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br> + </span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support +for <b>STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices</b>. </span><span style="font-size: 10pt;"><o:p></o:p></span></li> + +</ul> +<ol style="margin-top: 0in;" start="2" type="1"> +<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol> + <ul> + <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li> + </ul> + <ol style="margin-top: 0in; list-style-type: decimal;" start="3"> + <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li> + + </ol> + + <ul style="margin-top: 0in;" type="disc"> + + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br> + </li> + <ul> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br> + </span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.<br> + </span></li> + </ul> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br> + <span style="font-size: 10pt; font-family: Verdana;"></span></li> + <ul> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br> + <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default + </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br> + </span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br> + </span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br> + </span></li> + </ul> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li> + <ul> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new +startup files for STM32 Low-density Value line devices: + <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup +files for STM32 Medium-density Value line devices: + <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br> +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br> +</span></li> + <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br> +</span></li> + </ul> + + </ul> + +<ul style="margin-top: 0in;" type="disc"> +</ul> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2> +<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.</span> +<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;"> +<hr align="center" size="2" width="100%"></span></div> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For +complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers +visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +</div> +<p class="MsoNormal"><o:p> </o:p></p> +</div> +</body></html>
\ No newline at end of file diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s new file mode 100644 index 0000000..7e2f3f6 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s new file mode 100644 index 0000000..15a7768 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s @@ -0,0 +1,375 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..0eb5010 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s @@ -0,0 +1,311 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s new file mode 100644 index 0000000..5a5cd49 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s @@ -0,0 +1,474 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..d226209 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM32100E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s new file mode 100644 index 0000000..9c29765 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s @@ -0,0 +1,514 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Connectivity line devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..7cde5bb --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s @@ -0,0 +1,376 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..b4af984 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s @@ -0,0 +1,401 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c new file mode 100644 index 0000000..c0489e7 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c @@ -0,0 +1,1100 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h new file mode 100644 index 0000000..c18f853 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h @@ -0,0 +1,6205 @@ +/** + ****************************************************************************** + * @file stm32f30x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F30x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x + * @{ + */ + +#ifndef __STM32F30x_H +#define __STM32F30x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F30X) + #define STM32F30X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F30X) + #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + + +/** + * @brief STM32F30x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F30X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ + + +/** + * @brief STM32F30X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ + COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f30x.h" /* STM32F30x System Header */ +#include <stdint.h> + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ + __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ + +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ + __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ + uint16_t RESERVED0; /*!< Reserved, 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ + __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ + __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */ + __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */ +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + uint16_t RESERVED1; /*!< Reserved, 0x12 */ + __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + uint16_t RESERVED2; /*!< Reserved, 0x16 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ + __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint16_t RESERVED3; /*!< Reserved, 0x2A */ +}GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ +} OPAMP_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +}I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ +} RTC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + uint16_t RESERVED1; /*!< Reserved, 0x0E */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) +#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020) +#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024) +#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028) +#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C) +#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030) +#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040) +#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) +#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000) +#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008) +#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C) +#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030) +#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044) +#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058) +#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C) +#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400) +#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408) +#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C) +#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430) +#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444) +#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458) +#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000) +#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) + +/*!< AHB3 peripherals */ +#define ADC1_BASE (AHB3PERIPH_BASE + 0x0000) +#define ADC2_BASE (AHB3PERIPH_BASE + 0x0100) +#define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300) +#define ADC3_BASE (AHB3PERIPH_BASE + 0x0400) +#define ADC4_BASE (AHB3PERIPH_BASE + 0x0500) +#define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700) + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) +#define COMP5 ((COMP_TypeDef *) COMP5_BASE) +#define COMP6 ((COMP_TypeDef *) COMP6_BASE) +#define COMP7 ((COMP_TypeDef *) COMP7_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC4 ((ADC_TypeDef *) ADC4_BASE) +#define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE) +#define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter SAR (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ +#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ +#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ +#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */ +#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */ +#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */ +#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ +#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ +#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ + +#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */ + +#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ +#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ +#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ +#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ + +#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ +#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ + +#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ +#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ +#define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */ +#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ +#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ +#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ + +#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */ +#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ +#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ +#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ +#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ +#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ +#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ +#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ + +#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ +#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ +#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ + +#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ +#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ +#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ + +#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ +#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ +#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ + +#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ +#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ +#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ + +#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ +#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ +#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ + +#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ +#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ +#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ + +#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ +#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ +#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ + +#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ +#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ +#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ + +#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ +#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ +#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ + +/******************** Bit definition for ADC_TR1 register ********************/ +#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ +#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ +#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ +#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ +#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ +#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ +#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ +#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ +#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ +#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ +#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ +#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ + +#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ +#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ +#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ +#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ +#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ +#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ +#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ +#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ +#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ +#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ +#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ +#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ + +/******************** Bit definition for ADC_TR2 register ********************/ +#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ +#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ +#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ +#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ +#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ +#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ +#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ +#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ + +#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ +#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ +#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ +#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ +#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ +#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ +#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ +#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ + +/******************** Bit definition for ADC_TR3 register ********************/ +#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ +#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ +#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ +#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ +#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ +#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ +#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ +#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ + +#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ +#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ +#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ +#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ +#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ +#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ +#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ +#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */ +#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ + +#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ +#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ +#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ +#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ +#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ + +#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ +#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ +#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ +#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ +#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ + +#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ +#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ +#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ +#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ +#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ + +#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ +#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ +#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ +#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ +#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ +#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ +#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ +#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ +#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ + +#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ +#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ +#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ +#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ +#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ + +#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ +#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ +#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ +#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ +#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ + +#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ +#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ +#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ +#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ +#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ + +#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ +#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ +#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ +#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ +#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ + +#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR3_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ +#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ +#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ +#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ +#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ +#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ +#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ +#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ +#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ +#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ +#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ +#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ +#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ +#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ +#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ +#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ +#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ + +#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ +#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ +#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ +#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ + +#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ +#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ + +#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ +#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ +#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ +#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ +#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ +#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ +#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ +#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ +#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ +#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ +#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ +#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ + +#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ +#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ +#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ +#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ +#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ + +#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ +#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ +#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ +#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ +#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ +#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ +#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ +#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ +#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ +#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ +#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ +#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ + +#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ +#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ +#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ +#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ +#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ + +#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ +#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ +#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ +#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ +#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ +#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ +#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ +#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ +#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ +#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ +#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ +#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ + +#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ +#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ +#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ +#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ +#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ + +#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ +#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ +#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ +#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ +#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ +#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ +#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ +#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ +#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ +#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ +#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ +#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ + +#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ +#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ +#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ +#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ +#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ + +#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */ +#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */ +#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */ +#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */ +#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */ +#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */ +#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */ +#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */ +#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */ +#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */ +#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */ +#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */ +#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */ +#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */ +#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */ +#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */ +#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */ +#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */ +#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */ +#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */ +#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */ +#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */ +#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */ +#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */ +#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */ +#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */ +#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */ +#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */ +#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */ +#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */ +#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */ +#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */ +#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */ +#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */ +#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */ +#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */ +#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */ +#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */ +#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */ +#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */ +#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */ +#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */ +#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */ +#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */ +#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */ +#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */ +#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */ +#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */ +#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */ +#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */ +#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */ +#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ +#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ +#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ +#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ +#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ +#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ +#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ +#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ +#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ +#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ +#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ +#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ +#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ +#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC12_CSR register ********************/ +#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ +#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ +#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ +#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ +#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ +#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ +#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ +#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ +#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ +#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ +#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ +#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ +#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ +#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ +#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ +#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC34_CSR register ********************/ +#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ +#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ +#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ +#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ +#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ +#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ +#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ +#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ +#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ +#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ +#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ +#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ +#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ +#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ +#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ +#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ +#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ +#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ +#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ +#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ +#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ +#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ +#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ +#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ +#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ +#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ +#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ +#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ +#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ +#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ +#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ +#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ +#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ +#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ +#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ +#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ +#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ +#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ +#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ +#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ +#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ + +#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ +#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ +#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ +#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ +#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ + +#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ +#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ +#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ +#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ + +#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ +#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ +#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ + +#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ +#define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ +#define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register ********************/ +#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ +#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ +#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ +#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ +#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ +#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ +#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ +#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ +#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ +#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ +#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ +#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ +#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ +#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ +#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ +#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ +#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ + +#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ +#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ +#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ +#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ +#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ +#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ +#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ +#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ +#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ +#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ +#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ +#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ +#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ +#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ +#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ +#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ +#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ + +/******************** Bit definition for ADC_CDR register ********************/ +#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ +#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ +#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ +#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ +#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ +#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ +#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ +#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ +#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ +#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ +#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ +#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ +#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ +#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ +#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ +#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ +#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ + +#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ +#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ +#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ +#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ +#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ +#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ +#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ +#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ +#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ +#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ +#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ +#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ +#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ +#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ +#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ +#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ +#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP1_CSR register ***************/ +#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */ +#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ +#define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */ +#define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */ +#define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */ +#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */ +#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */ +#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */ +#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */ +#define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */ +#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */ +#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */ +#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */ +#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */ +#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */ +#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */ +#define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */ +#define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */ +#define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */ +#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */ +#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */ +#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */ +#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */ +#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */ +#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */ + +/********************** Bit definition for COMP2_CSR register ***************/ +#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */ +#define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */ +#define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */ +#define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */ +#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */ +#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */ +#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */ +#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */ +#define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */ +#define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */ +#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */ +#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */ +#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */ +#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */ +#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */ +#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */ +#define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */ +#define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */ +#define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */ +#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */ +#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */ +#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */ +#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */ +#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ +#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ + +/********************** Bit definition for COMP3_CSR register ***************/ +#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */ +#define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */ +#define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */ +#define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */ +#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */ +#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */ +#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */ +#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */ +#define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */ +#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */ +#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */ +#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */ +#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */ +#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */ +#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */ +#define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */ +#define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */ +#define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */ +#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */ +#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */ +#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */ +#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */ +#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */ +#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */ + +/********************** Bit definition for COMP4_CSR register ***************/ +#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */ +#define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */ +#define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */ +#define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */ +#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */ +#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */ +#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */ +#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */ +#define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */ +#define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */ +#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */ +#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */ +#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */ +#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */ +#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */ +#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */ +#define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */ +#define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */ +#define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */ +#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */ +#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */ +#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */ +#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */ +#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */ +#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */ + +/********************** Bit definition for COMP5_CSR register ***************/ +#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */ +#define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */ +#define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */ +#define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */ +#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */ +#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */ +#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */ +#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */ +#define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */ +#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */ +#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */ +#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */ +#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */ +#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */ +#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */ +#define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */ +#define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */ +#define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */ +#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */ +#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */ +#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */ +#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */ +#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */ +#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */ + +/********************** Bit definition for COMP6_CSR register ***************/ +#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */ +#define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */ +#define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */ +#define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */ +#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */ +#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */ +#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */ +#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */ +#define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */ +#define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */ +#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */ +#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */ +#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */ +#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */ +#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */ +#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */ +#define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */ +#define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */ +#define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */ +#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */ +#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */ +#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */ +#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */ +#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */ +#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */ + +/********************** Bit definition for COMP7_CSR register ***************/ +#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */ +#define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */ +#define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */ +#define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */ +#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */ +#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */ +#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */ +#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */ +#define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */ +#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */ +#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */ +#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */ +#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */ +#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */ +#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */ +#define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */ +#define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */ +#define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */ +#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */ +#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */ +#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */ +#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */ +#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */ +#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ +#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ +#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ +#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ +#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ +#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ +#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ +#define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */ +#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */ +#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */ +#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */ +#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */ +#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */ +#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */ +#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */ +#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */ +#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */ +#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */ +#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */ +#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMP1_CSR register ***************/ +#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */ +#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ +#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ +#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ +#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ +#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ +#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ +#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ +#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ +#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ +#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ +#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ +#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ +#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ +#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ +#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ +#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ +#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ +#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ +#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ + +/********************* Bit definition for OPAMP2_CSR register ***************/ +#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */ +#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ +#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ +#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ +#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ +#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ +#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ +#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ +#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ +#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ +#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ +#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ +#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ +#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ +#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ +#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ +#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ +#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ +#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ +#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ + +/********************* Bit definition for OPAMP3_CSR register ***************/ +#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */ +#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ +#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ +#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ +#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ +#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ +#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ +#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ +#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ +#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ +#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ +#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ +#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ +#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ +#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ +#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ +#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ +#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ +#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ +#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ + +/********************* Bit definition for OPAMP4_CSR register ***************/ +#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */ +#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ +#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ +#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ +#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ +#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ +#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ +#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ +#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ +#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ +#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ +#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ +#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ +#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ +#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ +#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ +#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ +#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ +#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ +#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ + +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */ +#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ +#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ +#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ +#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ +#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ +#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ +#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ +#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ +#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ +#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ +#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ +#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ +#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ +#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ +#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ +#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ +#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ + + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN ) */ +/* */ +/******************************************************************************/ +/*!<CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ + +/*!<Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/*!<CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ +#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ +#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ +#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) + +/******************** Bit definition for DBGMCU_CR register *****************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ + +/******************** Bit definition for DBGMCU_APB1_FZ register ************/ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) +#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) +#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) +#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) + +/******************** Bit definition for DBGMCU_APB2_FZ register ************/ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) +#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ +#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ +#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ +#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ +#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller (EXTI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ +#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ +#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ +#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ +#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ +#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ +#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ +#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ +#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ +#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ +#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ +#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ +#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ +#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ +#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ +#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ +#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ +#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ +#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ +#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ +#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ +#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ +#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ +#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ +#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ +#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ +#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ +#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ +#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ +#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ +#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ +#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ +#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +#define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */ +#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ +#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ +#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ +#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ +#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ +#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ +#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ +#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ + +#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ +#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ +#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for OB_RDP register **********************/ +#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for OB_USER register *********************/ +#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ +/******************************************************************************/ +/* */ +/* General Purpose I/O (GPIO) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODER0 ((uint32_t)0x00000003) +#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) +#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) +#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) +#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) +#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) +#define GPIO_MODER_MODER2 ((uint32_t)0x00000030) +#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) +#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) +#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) +#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) +#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) +#define GPIO_MODER_MODER4 ((uint32_t)0x00000300) +#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) +#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) +#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) +#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) +#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) +#define GPIO_MODER_MODER6 ((uint32_t)0x00003000) +#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) +#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) +#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) +#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) +#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) +#define GPIO_MODER_MODER8 ((uint32_t)0x00030000) +#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) +#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) +#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) +#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) +#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) +#define GPIO_MODER_MODER10 ((uint32_t)0x00300000) +#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) +#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) +#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) +#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) +#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) +#define GPIO_MODER_MODER12 ((uint32_t)0x03000000) +#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) +#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) +#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) +#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) +#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) +#define GPIO_MODER_MODER14 ((uint32_t)0x30000000) +#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) +#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) +#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) +#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) +#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) + + +/****************** Bit definition for GPIO_OTYPER register *****************/ +#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) +#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) +#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) +#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) +#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) +#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) +#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) +#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) +#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) +#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) +#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) +#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) +#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) +#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) +#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) +#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) + + +/**************** Bit definition for GPIO_OSPEEDR register ******************/ +#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) +#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) +#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) +#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) +#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) +#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) +#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) +#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) +#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) +#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) +#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) +#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) +#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) +#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) +#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) +#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) +#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) +#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) +#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) +#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) +#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) +#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) +#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) +#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) +#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) +#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) +#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) +#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) +#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) +#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) +#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) +#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) +#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) +#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) +#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) +#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) +#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) +#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) +#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) +#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) +#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) +#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) +#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) +#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) +#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) +#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) +#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) +#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) + +/******************* Bit definition for GPIO_PUPDR register ******************/ +#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) +#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) +#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) +#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) +#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) +#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) +#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) +#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) +#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) +#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) +#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) +#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) +#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) +#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) +#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) +#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) +#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) +#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) +#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) +#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) +#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) +#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) +#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) +#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) +#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) +#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) +#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) +#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) +#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) +#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) +#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) +#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) +#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) +#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) +#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) +#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) +#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) +#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) +#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) +#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) +#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) +#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) +#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) +#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) +#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) +#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) +#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) +#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) + +/******************* Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_0 ((uint32_t)0x00000001) +#define GPIO_IDR_1 ((uint32_t)0x00000002) +#define GPIO_IDR_2 ((uint32_t)0x00000004) +#define GPIO_IDR_3 ((uint32_t)0x00000008) +#define GPIO_IDR_4 ((uint32_t)0x00000010) +#define GPIO_IDR_5 ((uint32_t)0x00000020) +#define GPIO_IDR_6 ((uint32_t)0x00000040) +#define GPIO_IDR_7 ((uint32_t)0x00000080) +#define GPIO_IDR_8 ((uint32_t)0x00000100) +#define GPIO_IDR_9 ((uint32_t)0x00000200) +#define GPIO_IDR_10 ((uint32_t)0x00000400) +#define GPIO_IDR_11 ((uint32_t)0x00000800) +#define GPIO_IDR_12 ((uint32_t)0x00001000) +#define GPIO_IDR_13 ((uint32_t)0x00002000) +#define GPIO_IDR_14 ((uint32_t)0x00004000) +#define GPIO_IDR_15 ((uint32_t)0x00008000) + +/****************** Bit definition for GPIO_ODR register ********************/ +#define GPIO_ODR_0 ((uint32_t)0x00000001) +#define GPIO_ODR_1 ((uint32_t)0x00000002) +#define GPIO_ODR_2 ((uint32_t)0x00000004) +#define GPIO_ODR_3 ((uint32_t)0x00000008) +#define GPIO_ODR_4 ((uint32_t)0x00000010) +#define GPIO_ODR_5 ((uint32_t)0x00000020) +#define GPIO_ODR_6 ((uint32_t)0x00000040) +#define GPIO_ODR_7 ((uint32_t)0x00000080) +#define GPIO_ODR_8 ((uint32_t)0x00000100) +#define GPIO_ODR_9 ((uint32_t)0x00000200) +#define GPIO_ODR_10 ((uint32_t)0x00000400) +#define GPIO_ODR_11 ((uint32_t)0x00000800) +#define GPIO_ODR_12 ((uint32_t)0x00001000) +#define GPIO_ODR_13 ((uint32_t)0x00002000) +#define GPIO_ODR_14 ((uint32_t)0x00004000) +#define GPIO_ODR_15 ((uint32_t)0x00008000) + +/****************** Bit definition for GPIO_BSRR register ********************/ +#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) +#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) +#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) +#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) +#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) +#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) +#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) +#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) +#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) +#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) +#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) +#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) +#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) +#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) +#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) +#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) +#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) +#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) +#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) +#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) +#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) +#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) +#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) +#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) +#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) +#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) +#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) +#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) +#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) +#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) +#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) +#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) + +/****************** Bit definition for GPIO_LCKR register ********************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) + +/****************** Bit definition for GPIO_AFRL register ********************/ +#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) +#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) +#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) +#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) +#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) +#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) +#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) +#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) + +/****************** Bit definition for GPIO_AFRH register ********************/ +#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) +#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) +#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) +#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) +#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) +#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) +#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) +#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) + +/****************** Bit definition for GPIO_BRR register *********************/ +#define GPIO_BRR_BR_0 ((uint32_t)0x00000001) +#define GPIO_BRR_BR_1 ((uint32_t)0x00000002) +#define GPIO_BRR_BR_2 ((uint32_t)0x00000004) +#define GPIO_BRR_BR_3 ((uint32_t)0x00000008) +#define GPIO_BRR_BR_4 ((uint32_t)0x00000010) +#define GPIO_BRR_BR_5 ((uint32_t)0x00000020) +#define GPIO_BRR_BR_6 ((uint32_t)0x00000040) +#define GPIO_BRR_BR_7 ((uint32_t)0x00000080) +#define GPIO_BRR_BR_8 ((uint32_t)0x00000100) +#define GPIO_BRR_BR_9 ((uint32_t)0x00000200) +#define GPIO_BRR_BR_10 ((uint32_t)0x00000400) +#define GPIO_BRR_BR_11 ((uint32_t)0x00000800) +#define GPIO_BRR_BR_12 ((uint32_t)0x00001000) +#define GPIO_BRR_BR_13 ((uint32_t)0x00002000) +#define GPIO_BRR_BR_14 ((uint32_t)0x00004000) +#define GPIO_BRR_BR_15 ((uint32_t)0x00008000) + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ +#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ +#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ +#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ +#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ +#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ +#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ +#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ +#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ +#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ +#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *****************/ +#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ +#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *****************/ +#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ +#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ +#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ +#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ +#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ +#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ +#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ +#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ +#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ +#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ +#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register ********************/ +#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */ + +#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) + +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) +#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ +#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ +#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ +#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ +#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ + +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) +#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ +#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ +#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ +#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ +#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ +#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ +#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ +#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ + +#define RCC_CR_HSEON ((uint32_t)0x00010000) +#define RCC_CR_HSERDY ((uint32_t)0x00020000) +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) +#define RCC_CR_CSSON ((uint32_t)0x00080000) + +#define RCC_CR_PLLON ((uint32_t)0x01000000) +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ +#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< USB configuration */ +#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */ + +/*!< I2S configuration */ +#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */ +#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */ +#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + +#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */ + +/********************* Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +/****************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */ +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */ + +/****************** Bit definition for RCC_APB1RSTR register ******************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */ +#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ +#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */ +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */ +#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ +#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */ +#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */ +#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */ +#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */ +#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */ +#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */ +#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */ +#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */ +#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */ + +/****************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */ +#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1ENR_UART3EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */ +#define RCC_APB1ENR_UART4EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ +#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */ + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC configuration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ****************/ +#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */ +#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */ +#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */ +#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */ +#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF reset */ +#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */ +#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */ +#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ +#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ +#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ +#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ +#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ +#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ +#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ +#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ +#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ +#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ +#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ +#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ +#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ +#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ +#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ +#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ +#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ +#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< ADCPRE12 configuration */ +#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */ +#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */ +#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */ + +#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ +#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */ +#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */ +#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */ +#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */ +#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */ +#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */ +#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */ +#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */ +#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */ +#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */ +#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */ +#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */ + +/*!< ADCPRE34 configuration */ +#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */ +#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */ +#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */ + +#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ +#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */ +#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */ +#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */ +#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */ +#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */ +#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */ +#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */ +#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */ +#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */ +#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */ +#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */ +#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */ + +/******************* Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */ +#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */ +#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ +#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */ + +#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */ +#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */ +#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */ + +#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ +#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */ +#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */ +#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */ +#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_PM ((uint32_t)0x00400000) +#define RTC_TR_HT ((uint32_t)0x00300000) +#define RTC_TR_HT_0 ((uint32_t)0x00100000) +#define RTC_TR_HT_1 ((uint32_t)0x00200000) +#define RTC_TR_HU ((uint32_t)0x000F0000) +#define RTC_TR_HU_0 ((uint32_t)0x00010000) +#define RTC_TR_HU_1 ((uint32_t)0x00020000) +#define RTC_TR_HU_2 ((uint32_t)0x00040000) +#define RTC_TR_HU_3 ((uint32_t)0x00080000) +#define RTC_TR_MNT ((uint32_t)0x00007000) +#define RTC_TR_MNT_0 ((uint32_t)0x00001000) +#define RTC_TR_MNT_1 ((uint32_t)0x00002000) +#define RTC_TR_MNT_2 ((uint32_t)0x00004000) +#define RTC_TR_MNU ((uint32_t)0x00000F00) +#define RTC_TR_MNU_0 ((uint32_t)0x00000100) +#define RTC_TR_MNU_1 ((uint32_t)0x00000200) +#define RTC_TR_MNU_2 ((uint32_t)0x00000400) +#define RTC_TR_MNU_3 ((uint32_t)0x00000800) +#define RTC_TR_ST ((uint32_t)0x00000070) +#define RTC_TR_ST_0 ((uint32_t)0x00000010) +#define RTC_TR_ST_1 ((uint32_t)0x00000020) +#define RTC_TR_ST_2 ((uint32_t)0x00000040) +#define RTC_TR_SU ((uint32_t)0x0000000F) +#define RTC_TR_SU_0 ((uint32_t)0x00000001) +#define RTC_TR_SU_1 ((uint32_t)0x00000002) +#define RTC_TR_SU_2 ((uint32_t)0x00000004) +#define RTC_TR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_YT ((uint32_t)0x00F00000) +#define RTC_DR_YT_0 ((uint32_t)0x00100000) +#define RTC_DR_YT_1 ((uint32_t)0x00200000) +#define RTC_DR_YT_2 ((uint32_t)0x00400000) +#define RTC_DR_YT_3 ((uint32_t)0x00800000) +#define RTC_DR_YU ((uint32_t)0x000F0000) +#define RTC_DR_YU_0 ((uint32_t)0x00010000) +#define RTC_DR_YU_1 ((uint32_t)0x00020000) +#define RTC_DR_YU_2 ((uint32_t)0x00040000) +#define RTC_DR_YU_3 ((uint32_t)0x00080000) +#define RTC_DR_WDU ((uint32_t)0x0000E000) +#define RTC_DR_WDU_0 ((uint32_t)0x00002000) +#define RTC_DR_WDU_1 ((uint32_t)0x00004000) +#define RTC_DR_WDU_2 ((uint32_t)0x00008000) +#define RTC_DR_MT ((uint32_t)0x00001000) +#define RTC_DR_MU ((uint32_t)0x00000F00) +#define RTC_DR_MU_0 ((uint32_t)0x00000100) +#define RTC_DR_MU_1 ((uint32_t)0x00000200) +#define RTC_DR_MU_2 ((uint32_t)0x00000400) +#define RTC_DR_MU_3 ((uint32_t)0x00000800) +#define RTC_DR_DT ((uint32_t)0x00000030) +#define RTC_DR_DT_0 ((uint32_t)0x00000010) +#define RTC_DR_DT_1 ((uint32_t)0x00000020) +#define RTC_DR_DU ((uint32_t)0x0000000F) +#define RTC_DR_DU_0 ((uint32_t)0x00000001) +#define RTC_DR_DU_1 ((uint32_t)0x00000002) +#define RTC_DR_DU_2 ((uint32_t)0x00000004) +#define RTC_DR_DU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_COE ((uint32_t)0x00800000) +#define RTC_CR_OSEL ((uint32_t)0x00600000) +#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) +#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) +#define RTC_CR_POL ((uint32_t)0x00100000) +#define RTC_CR_COSEL ((uint32_t)0x00080000) +#define RTC_CR_BCK ((uint32_t)0x00040000) +#define RTC_CR_SUB1H ((uint32_t)0x00020000) +#define RTC_CR_ADD1H ((uint32_t)0x00010000) +#define RTC_CR_TSIE ((uint32_t)0x00008000) +#define RTC_CR_WUTIE ((uint32_t)0x00004000) +#define RTC_CR_ALRBIE ((uint32_t)0x00002000) +#define RTC_CR_ALRAIE ((uint32_t)0x00001000) +#define RTC_CR_TSE ((uint32_t)0x00000800) +#define RTC_CR_WUTE ((uint32_t)0x00000400) +#define RTC_CR_ALRBE ((uint32_t)0x00000200) +#define RTC_CR_ALRAE ((uint32_t)0x00000100) +#define RTC_CR_FMT ((uint32_t)0x00000040) +#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) +#define RTC_CR_REFCKON ((uint32_t)0x00000010) +#define RTC_CR_TSEDGE ((uint32_t)0x00000008) +#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) +#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) +#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) +#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) + +/******************** Bits definition for RTC_ISR register ******************/ +#define RTC_ISR_RECALPF ((uint32_t)0x00010000) +#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) +#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) +#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) +#define RTC_ISR_TSOVF ((uint32_t)0x00001000) +#define RTC_ISR_TSF ((uint32_t)0x00000800) +#define RTC_ISR_WUTF ((uint32_t)0x00000400) +#define RTC_ISR_ALRBF ((uint32_t)0x00000200) +#define RTC_ISR_ALRAF ((uint32_t)0x00000100) +#define RTC_ISR_INIT ((uint32_t)0x00000080) +#define RTC_ISR_INITF ((uint32_t)0x00000040) +#define RTC_ISR_RSF ((uint32_t)0x00000020) +#define RTC_ISR_INITS ((uint32_t)0x00000010) +#define RTC_ISR_SHPF ((uint32_t)0x00000008) +#define RTC_ISR_WUTWF ((uint32_t)0x00000004) +#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) +#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) +#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) +#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) +#define RTC_ALRMAR_DT ((uint32_t)0x30000000) +#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) +#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) +#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) +#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) +#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) +#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) +#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) +#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) +#define RTC_ALRMAR_PM ((uint32_t)0x00400000) +#define RTC_ALRMAR_HT ((uint32_t)0x00300000) +#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) +#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) +#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) +#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) +#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) +#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) +#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) +#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) +#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) +#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) +#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) +#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) +#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) +#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) +#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) +#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) +#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) +#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) +#define RTC_ALRMAR_ST ((uint32_t)0x00000070) +#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) +#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) +#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) +#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) +#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) +#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) +#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) +#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) +#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) +#define RTC_ALRMBR_DT ((uint32_t)0x30000000) +#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) +#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) +#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) +#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) +#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) +#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) +#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) +#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) +#define RTC_ALRMBR_PM ((uint32_t)0x00400000) +#define RTC_ALRMBR_HT ((uint32_t)0x00300000) +#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) +#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) +#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) +#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) +#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) +#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) +#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) +#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) +#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) +#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) +#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) +#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) +#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) +#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) +#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) +#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) +#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) +#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) +#define RTC_ALRMBR_ST ((uint32_t)0x00000070) +#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) +#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) +#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) +#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) +#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) +#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) +#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) +#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY ((uint32_t)0x000000FF) + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) +#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM ((uint32_t)0x00400000) +#define RTC_TSTR_HT ((uint32_t)0x00300000) +#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) +#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) +#define RTC_TSTR_HU ((uint32_t)0x000F0000) +#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) +#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) +#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) +#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) +#define RTC_TSTR_MNT ((uint32_t)0x00007000) +#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) +#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) +#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) +#define RTC_TSTR_MNU ((uint32_t)0x00000F00) +#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) +#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) +#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) +#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) +#define RTC_TSTR_ST ((uint32_t)0x00000070) +#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) +#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) +#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) +#define RTC_TSTR_SU ((uint32_t)0x0000000F) +#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) +#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) +#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) +#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU ((uint32_t)0x0000E000) +#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSDR_MT ((uint32_t)0x00001000) +#define RTC_TSDR_MU ((uint32_t)0x00000F00) +#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) +#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) +#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) +#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) +#define RTC_TSDR_DT ((uint32_t)0x00000030) +#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) +#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) +#define RTC_TSDR_DU ((uint32_t)0x0000000F) +#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) +#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) +#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) +#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CAL register *****************/ +#define RTC_CALR_CALP ((uint32_t)0x00008000) +#define RTC_CALR_CALW8 ((uint32_t)0x00004000) +#define RTC_CALR_CALW16 ((uint32_t)0x00002000) +#define RTC_CALR_CALM ((uint32_t)0x000001FF) +#define RTC_CALR_CALM_0 ((uint32_t)0x00000001) +#define RTC_CALR_CALM_1 ((uint32_t)0x00000002) +#define RTC_CALR_CALM_2 ((uint32_t)0x00000004) +#define RTC_CALR_CALM_3 ((uint32_t)0x00000008) +#define RTC_CALR_CALM_4 ((uint32_t)0x00000010) +#define RTC_CALR_CALM_5 ((uint32_t)0x00000020) +#define RTC_CALR_CALM_6 ((uint32_t)0x00000040) +#define RTC_CALR_CALM_7 ((uint32_t)0x00000080) +#define RTC_CALR_CALM_8 ((uint32_t)0x00000100) + +/******************** Bits definition for RTC_TAFCR register ****************/ +#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) +#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) +#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) +#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) +#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) +#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) +#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) +#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) +#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) +#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) +#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) +#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) +#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) +#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) +#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) +#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) +#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) +#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) +#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) +#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) +#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_BKP0R register ****************/ +#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP1R register ****************/ +#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP2R register ****************/ +#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP3R register ****************/ +#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP4R register ****************/ +#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP5R register ****************/ +#define RTC_BKP5R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP6R register ****************/ +#define RTC_BKP6R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP7R register ****************/ +#define RTC_BKP7R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP8R register ****************/ +#define RTC_BKP8R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP9R register ****************/ +#define RTC_BKP9R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP10R register ***************/ +#define RTC_BKP10R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP11R register ***************/ +#define RTC_BKP11R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP12R register ***************/ +#define RTC_BKP12R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP13R register ***************/ +#define RTC_BKP13R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP14R register ***************/ +#define RTC_BKP14R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP15R register ***************/ +#define RTC_BKP15R ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */ +#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */ +#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */ + +#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */ +#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */ +#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */ +#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */ +#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */ +#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */ +#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */ +#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */ +#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */ +#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */ +#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* System Configuration(SYSCFG) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for SYSCFG_CFGR1 register *****************/ +#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */ +#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */ +#define SYSCFG_CFGR1_DAC_TRIG_RMP ((uint32_t)0x00000080) /*!< DAC Trigger remap */ +#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */ +#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ +#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ +#define SYSCFG_CFGR1_TIM6DAC1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 DMA remap */ +#define SYSCFG_CFGR1_TIM7DAC2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC2 DMA remap */ +#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ +#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */ +#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */ +#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */ +#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */ +#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */ +#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */ +#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */ +#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */ +#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */ +#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */ +#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */ +#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */ + +/***************** Bit definition for SYSCFG_RCR register *******************/ +#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */ +#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */ +#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */ +#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */ +#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */ +#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */ +#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */ +#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */ + +/***************** Bit definition for SYSCFG_EXTICR1 register ***************/ +#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/** + * @brief EXTI0 configuration + */ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ + +/** + * @brief EXTI1 configuration + */ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ + +/** + * @brief EXTI2 configuration + */ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ + +/** + * @brief EXTI3 configuration + */ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ + +/***************** Bit definition for SYSCFG_EXTICR2 register ***************/ +#define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/** + * @brief EXTI4 configuration + */ +#define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ + +/** + * @brief EXTI5 configuration + */ +#define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ + +/** + * @brief EXTI6 configuration + */ +#define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ + +/** + * @brief EXTI7 configuration + */ +#define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ + +/***************** Bit definition for SYSCFG_EXTICR3 register ***************/ +#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/** + * @brief EXTI8 configuration + */ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ + +/** + * @brief EXTI9 configuration + */ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ + +/** + * @brief EXTI10 configuration + */ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ + +/** + * @brief EXTI11 configuration + */ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ + +/***************** Bit definition for SYSCFG_EXTICR4 register *****************/ +#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/** + * @brief EXTI12 configuration + */ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ + +/** + * @brief EXTI13 configuration + */ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ + +/** + * @brief EXTI14 configuration + */ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ + +/** + * @brief EXTI15 configuration + */ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ + +/***************** Bit definition for SYSCFG_CFGR2 register *****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ +#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */ +#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */ +#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */ +#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ + +#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ + +#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ +#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ +#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */ +#define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */ + +#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ + +#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ + +#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ + +#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ + +#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ +#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ +#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ +#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */ +#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */ +#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */ +#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */ + + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */ +#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */ +#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */ +#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */ + + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ + +#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ + +#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ +#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */ +#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */ +#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */ +#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */ +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ +#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */ +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_CCR5 register *******************/ +#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */ +#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */ +#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */ +#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */ + +/******************* Bit definition for TIM_CCR6 register *******************/ +#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ + +#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */ +#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */ +#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ +#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ + +#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */ +#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */ + +#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */ +#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ + +/******************* Bit definition for TIM16_OR register *********************/ +#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ +#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */ +#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */ + +/******************* Bit definition for TIM1_OR register *********************/ +#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ +#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ +#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ +#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ +#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ + +/******************* Bit definition for TIM8_OR register *********************/ +#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */ +#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ +#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ +#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ +#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ + +/****************** Bit definition for TIM_CCMR3 register *******************/ +#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */ +#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */ + +#define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */ + +#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ + +#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ +#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ +#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ +#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ +#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ +#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ +#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ +#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ +#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ +#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ +#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ +#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ +#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ +#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ +#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ +#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ +#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ +#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ +#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ +#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ +#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ +#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ +#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ +#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ +#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ +#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ +#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ +#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ +#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ +#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ +#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ +#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ +#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ +#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ +#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ +#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */ + + +/******************* Bit definition for USART_RTOR register *****************/ +#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ +#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ + +/******************* Bit definition for USART_RQR register ******************/ +#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ +#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ +#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ +#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ +#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ + +/******************* Bit definition for USART_ISR register ******************/ +#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ +#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ +#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ +#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ +#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ +#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ +#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ +#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ +#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ +#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ +#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ +#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ +#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ +#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ +#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ +#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ +#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ +#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ +#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ +#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ +#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ +#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ + +/******************* Bit definition for USART_ICR register ******************/ +#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ +#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ +#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ +#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ +#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ +#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ +#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ +#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ +#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ +#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ +#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ +#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ + +/******************* Bit definition for USART_RDR register ******************/ +#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ + +/******************* Bit definition for USART_TDR register ******************/ +#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f30x_conf.h" +#endif /* USE_STDPERIPH_DRIVER */ + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F30x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html new file mode 100644 index 0000000..26085fd --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html @@ 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class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900"> +<tbody> + <tr> + <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td> + </tr> +<tr style=""> +<td style="padding: 1.5pt;"> +<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release +Notes for STM32F30x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900"> +<tbody> +<tr> +<td style="padding: 0cm;" valign="top"> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2> +<ol style="margin-top: 0cm;" start="1" type="1"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F30x CMSIS +update History</a><o:p></o:p></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li> +</ol> +<span style="font-family: "Times New Roman";"></span> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F30x CMSIS +update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 04-September-2012<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F30x</span> devices</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span> + +<ul style="margin-top: 0in;" type="disc"> +</ul> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; 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You may obtain a copy of the License +at:<br><br></span></p> +<div style="text-align: center;"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"> +<a href="http://www.st.com/software_license_agreement_liberty_v2" target="_blank">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"></span></div><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"><br>Unless +required by applicable law or agreed to in writing, software distributed under +the License is distributed on an "AS IS" BASIS, <br>WITHOUT WARRANTIES OR +CONDITIONS OF ANY KIND, either express or implied. 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\ No newline at end of file diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c new file mode 100644 index 0000000..831bd65 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.c + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F30x devices, + * and is generated by the clock configuration tool + * stm32f30x_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f30x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f30x.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F30x device + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 9 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * USB Clock | DISABLE + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 2 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** @addtogroup STM32F30x_System_Private_Includes + * @{ + */ + +#include "stm32f30x.h" + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 72000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= (uint32_t)0xFF00FCCC; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 2 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/system_stm32f37x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/system_stm32f37x.h new file mode 100644 index 0000000..b9f3c92 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/system_stm32f37x.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file system_stm32f37x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f37x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F37X_H +#define __SYSTEM_STM32F37X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F37x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F37x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F37X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s new file mode 100644 index 0000000..f3951af --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s @@ -0,0 +1,460 @@ +/** + ****************************************************************************** + * @file startup_stm32f37x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief STM32F37x Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_TS_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word TIM18_DAC2_IRQHandler /* TIM18 and DAC2 */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC_Alarm_IRQHandler */ + .word CEC_IRQHandler /* CEC */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_DAC1_IRQHandler /* TIM6 and DAC1 Channel1 & channel2 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word SDADC1_IRQHandler /* SDADC1 */ + .word SDADC2_IRQHandler /* SDADC2 */ + .word SDADC3_IRQHandler /* SDADC3 */ + .word COMP_IRQHandler /* COMP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word USBWakeUp_IRQHandler /* USB Wakeup */ + .word 0 /* Resrved */ + .word TIM19_IRQHandler /*TIM19 */ + .word 0 /* Resrved */ + .word FPU_IRQHandler /* FPU */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak TIM18_DAC2_IRQHandler + .thumb_set TIM18_DAC2_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC1_IRQHandler + .thumb_set TIM6_DAC1_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak SDADC1_IRQHandler + .thumb_set SDADC1_IRQHandler,Default_Handler + + .weak SDADC2_IRQHandler + .thumb_set SDADC2_IRQHandler,Default_Handler + + .weak SDADC3_IRQHandler + .thumb_set SDADC3_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM19_IRQHandler + .thumb_set TIM19_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html new file mode 100644 index 0000000..7164799 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html @@ -0,0 +1,365 @@ +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> +<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head> + + + + + + + +<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"> +<link rel="File-List" href="Release_Notes%20%28package%29_files/filelist.xml"> +<link rel="Edit-Time-Data" href="Release_Notes%20%28package%29_files/editdata.mso"><!--[if !mso]> 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Roman"; mso-fareast-font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--> +<style type="disc"> +</style><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="45058"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head> +<body link="blue" vlink="blue"> +<div class="Section1"> +<p class="MsoNormal"><span style="font-family: Arial;"><br> +</span><span style="font-family: Arial;"><o:p></o:p></span></p> +<div align="center"> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900"> +<tbody> +<tr style=""> +<td style="padding: 0cm;" valign="top"> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900"> +<tbody> +<tr style=""> +<td style="padding: 1.5pt;"> + +<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release +Notes for<o:p></o:p> STM32L1xx CMSIS<br> +</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright +© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp"></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900"> +<tbody> +<tr style=""> +<td style="padding: 0cm;" valign="top"> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2> +<ol style="margin-top: 0cm;" start="1" type="1"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx CMSIS update history</a><o:p></o:p></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li> +</ol> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx CMSIS update history<o:p></o:p></span></h2> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 05-March-2012<o:p></o:p></span></h3> + <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> + + <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 191px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 24-January-2012<o:p></o:p></span></h3> + <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> + + <ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Alpha version for <span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span> devices.</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li> + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new product define: "#define STM32L1XX_MDP"</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new product define: "#define STM32L1XX_HD"</span></li> + + </ul> + + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the library version to V1.1.0<br> + </span></li> + </ul> + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new IRQ to support STM32L1XX_HD and </span><span style="font-size: 10pt; font-family: Verdana;">STM32L1XX_MDP </span><span style="font-size: 10pt; font-family: Verdana;">vector table</span></li> + </ul> + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new and update some Typedef to support new peripherals (AES, SDIO, OPAMP, FSMC, I2S)</span></li> + </ul> + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new peripherals address mapping</span></li> + </ul> + <ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update bits definition</span></li> + </ul> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_mdp.s</span>" for all toolchains</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_hd.s</span>" for all toolchains</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the RTC "<span style="font-weight: bold; font-style: italic;">CAL</span>" register name to "<span style="font-weight: bold; font-style: italic;">CALR</span>"</span></li> + <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update registers bits definitions.</span><span style="color: black;"><o:p> </o:p></span><br> + + </li> +</ul> + + +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 31-December-2010<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul> + +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.</span> +<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;"> +<hr align="center" size="2" width="100%"></span></div> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For +complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers +visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +</div> +<p class="MsoNormal"><o:p> </o:p></p> +</div> +</body></html>
\ No newline at end of file diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s new file mode 100644 index 0000000..91a0c7d --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s @@ -0,0 +1,376 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_md.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..c7d1e5e --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s @@ -0,0 +1,356 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_hd.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power High-density Devices vector +;* table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT COMP_ACQ_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +AES_IRQHandler +COMP_ACQ_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..a92913e --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s @@ -0,0 +1,544 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_hd.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power High-density Devices vector +;* table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + + PUBWEAK COMP_ACQ_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_ACQ_IRQHandler + B COMP_ACQ_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/annotated.html 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class="contents"> +<div class="textblock">Here are the data structures with brief descriptions:</div><table> + <tr><td class="indexkey"><a class="el" href="union_a_p_s_r___type.html">APSR_Type</a></td><td class="indexvalue">Union type to access the Application Program Status Register (APSR) </td></tr> + <tr><td class="indexkey"><a class="el" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a></td><td class="indexvalue">Union type to access the Control Registers (CONTROL) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_core_debug___type.html">CoreDebug_Type</a></td><td class="indexvalue">Structure type to access the Core Debug Register (CoreDebug) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_d_w_t___type.html">DWT_Type</a></td><td class="indexvalue">Structure type to access the Data Watchpoint and Trace Register (DWT) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_f_p_u___type.html">FPU_Type</a></td><td class="indexvalue">Structure type to access the Floating Point Unit (FPU) </td></tr> + <tr><td class="indexkey"><a class="el" href="union_i_p_s_r___type.html">IPSR_Type</a></td><td class="indexvalue">Union type to access the Interrupt Program Status Register (IPSR) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_i_t_m___type.html">ITM_Type</a></td><td class="indexvalue">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_m_p_u___type.html">MPU_Type</a></td><td class="indexvalue">Structure type to access the Memory Protection Unit (MPU) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_n_v_i_c___type.html">NVIC_Type</a></td><td class="indexvalue">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_s_c_b___type.html">SCB_Type</a></td><td class="indexvalue">Structure type to access the System Control Block (SCB) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a></td><td class="indexvalue">Structure type to access the System Control and ID Register not in the SCB </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_sys_tick___type.html">SysTick_Type</a></td><td class="indexvalue">Structure type to access the System Timer (SysTick) </td></tr> + <tr><td class="indexkey"><a class="el" href="struct_t_p_i___type.html">TPI_Type</a></td><td class="indexvalue">Structure type to access the Trace Port Interface Register (TPI) </td></tr> + <tr><td class="indexkey"><a class="el" href="unionx_p_s_r___type.html">xPSR_Type</a></td><td class="indexvalue">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr> +</table> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html new file mode 100644 index 0000000..463bf6b --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html @@ -0,0 +1,516 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Device Header File <device.h></title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-CORE +  <span id="projectnumber">Version 3.01</span> + </div> + <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('device_h_pg.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Device Header File <device.h> </div> </div> +</div> +<div class="contents"> +<div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p> +<ul> +<li><a class="el" href="device_h_pg.html#interrupt_number_sec">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li> +<li><a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li> +<li><a class="el" href="device_h_pg.html#device_access">Device Peripheral Access Layer</a> provides definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li> +<li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li> +</ul> +<p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</p> +<h2><a class="anchor" id="interrupt_number_sec"></a> +Interrupt Number Definition</h2> +<p><a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the enumeration <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device.</p> +<ul> +<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li> +<li>Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a>.</li> +</ul> +<p><b>Example:</b> </p> +<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p> +<div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn +{ +<span class="comment">/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/</span> + <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30" title="Exception 2: Non Maskable Interrupt.">NonMaskableInt_IRQn</a> = -14, + <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85" title="Exception 3: Hard Fault Interrupt.">HardFault_IRQn</a> = -13, + <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237" title="Exception 11: SV Call Interrupt.">SVCall_IRQn</a> = -5, + <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2" title="Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].">PendSV_IRQn</a> = -2, + <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7" title="Exception 15: System Tick Interrupt.">SysTick_IRQn</a> = -1, +<span class="comment">/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/</span> + WAKEUP0_IRQn = 0, + WAKEUP1_IRQn = 1, + WAKEUP2_IRQn = 2, + : : + : : + EINT1_IRQn = 30, + EINT0_IRQn = 31, +} <a class="code" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8" title="Definition of IRQn numbers.">IRQn_Type</a>; +</pre></div><h2><a class="anchor" id="core_config_sect"></a> +Configuration of the Processor and Core Peripherals</h2> +<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> configures the Cortex-M or SecurCore processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_<cpu>.h</b>.</p> +<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p> +<p><b>core_cm0.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm0plus.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM0PLUS_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm3.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM3_REV </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm4.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM4_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_sc000.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__SC000_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_sc300.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__SC300_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>Example</b> </p> +<p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CM4_REV 0x0001 </span><span class="comment">/* Core revision r0p1 */</span> +<span class="preprocessor">#define __MPU_PRESENT 1 </span><span class="comment">/* MPU present or not */</span> +<span class="preprocessor">#define __NVIC_PRIO_BITS 3 </span><span class="comment">/* Number of Bits used for Priority Levels */</span> +<span class="preprocessor">#define __Vendor_SysTickConfig 0 </span><span class="comment">/* Set to 1 if different SysTick Config is used */</span> +<span class="preprocessor">#define __FPU_PRESENT 1 </span><span class="comment">/* FPU present or not */</span> +. +. +<span class="preprocessor">#include <core_cm4.h></span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span> +</pre></div><h2><a class="anchor" id="core_version_sect"></a> +CMSIS Version and Processor Information</h2> +<p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> to verify a minimum version or ensure that the right processor core is used.</p> +<p><b>core_cm0.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __CM0_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_M (0x00) </span><span class="comment">/* Cortex-M Core */</span> +</pre></div><p><b>core_cm0plus.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __CM0P_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_M (0x00) </span><span class="comment">/* Cortex-M Core */</span> +</pre></div><p><b>core_cm3.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __CM3_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_M (0x03) </span><span class="comment">/* Cortex-M Core */</span> +</pre></div><p><b>core_cm4.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __CM4_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_M (0x04) </span><span class="comment">/* Cortex-M Core */</span> +</pre></div><p><b>core_sc000.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __SC000_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_SC (0) </span><span class="comment">/* Cortex secure core */</span> +</pre></div><p><b>core_sc300.h</b> </p> +<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span> +<span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span> +<span class="preprocessor">#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \</span> +<span class="preprocessor"> __SC300_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span> +... +<span class="preprocessor">#define __CORTEX_SC (300) </span><span class="comment">/* Cortex secure core */</span> +</pre></div><h2><a class="anchor" id="device_access"></a> +Device Peripheral Access Layer</h2> +<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains for each peripheral:</p> +<ul> +<li>Register Layout Typedef</li> +<li>Base Address</li> +<li>Access Definitions</li> +</ul> +<p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p> +<h2><a class="anchor" id="device_h_sec"></a> +Device.h Template File</h2> +<p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p> +<div class="fragment"><pre class="fragment">/**************************************************************************//** + * @file <Device>.h + * @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for + * Device <Device> + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ +#define <Device>_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* ToDo: replace '<Device>' with your device name; add your doxyGen comment */ +/** @addtogroup <Device>_Definitions <Device> Definitions + This file defines all structures and symbols for <Device>: + - registers and bitfields + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup <Device>_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M# Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M# Processor Exceptions Numbers ***************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + +/****** Device Specific Interrupt Numbers ********************************************************/ +/* ToDo: add here your device specific external interrupt numbers + according the interrupt handlers defined in startup_Device.s + eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ + <DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M# Processor and Core Peripherals */ +/* ToDo: set the defines according your Device */ +/* ToDo: define the correct core revision + __CM0_REV if your device is a CORTEX-M0 device + __CM3_REV if your device is a CORTEX-M3 device + __CM4_REV if your device is a CORTEX-M4 device */ +#define __CM#_REV 0x0201 /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4 */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/*@}*/ /* end of group <Device>_CMSIS */ + + +/* ToDo: include the correct core_cm#.h file + core_cm0.h if your device is a CORTEX-M0 device + core_cm3.h if your device is a CORTEX-M3 device + core_cm4.h if your device is a CORTEX-M4 device */ +#include <core_cm#.h> /* Cortex-M# processor and core peripherals */ +/* ToDo: include your system_<Device>.h file + replace '<Device>' with your device name */ +#include "system_<Device>.h" /* <Device> System include file */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +/** @addtogroup <Device>_Peripherals <Device> Peripherals + <Device> Device Specific Peripheral registers structures + @{ +*/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/* ToDo: add here your device specific peripheral access structure typedefs + following is an example for a timer */ + +/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/ +/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR) + @{ +*/ +typedef struct +{ + __IO uint32_t EN; /*!< Offset: 0x0000 Timer Enable Register */ + __IO uint32_t RUN; /*!< Offset: 0x0004 Timer RUN Register */ + __IO uint32_t CR; /*!< Offset: 0x0008 Timer Control Register */ + __IO uint32_t MOD; /*!< Offset: 0x000C Timer Mode Register */ + uint32_t RESERVED0[1]; + __IO uint32_t ST; /*!< Offset: 0x0014 Timer Status Register */ + __IO uint32_t IM; /*!< Offset: 0x0018 Interrupt Mask Register */ + __IO uint32_t UC; /*!< Offset: 0x001C Timer Up Counter Register */ + __IO uint32_t RG0 /*!< Offset: 0x0020 Timer Register */ + uint32_t RESERVED1[2]; + __IO uint32_t CP; /*!< Offset: 0x002C Capture register */ +} <DeviceAbbreviation>_TMR_TypeDef; +/*@}*/ /* end of group <Device>_TMR */ + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/*@}*/ /* end of group <Device>_Peripherals */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* ToDo: add here your device peripherals base addresses + following is an example for timer */ +/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping + @{ +*/ + +/* Peripheral and SRAM base address */ +#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +/* Peripheral memory map */ +#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */ +#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */ +#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */ +/*@}*/ /* end of group <Device>_MemoryMap */ + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +/* ToDo: add here your device peripherals pointer definitions + following is an example for timer */ + +/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration + @{ +*/ + +#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) +#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) +#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) +/*@}*/ /* end of group <Device>_PeripheralDecl */ + +/*@}*/ /* end of group <Device>_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* <Device>_H */ +</pre></div> </div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="_templates_pg.html">Template Files</a> </li> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. 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href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a> +</li> +<li>__disable_fault_irq() +: <a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a> +</li> +<li>__disable_irq() +: <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">Ref_CoreReg.txt</a> +</li> +<li>__DMB() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">Ref_cmInstr.txt</a> +</li> +<li>__DSB() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a> +</li> +<li>__enable_fault_irq() +: <a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a> +</li> +<li>__enable_irq() +: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a> +</li> +<li>__get_APSR() +: <a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a> +</li> +<li>__get_BASEPRI() +: <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">Ref_CoreReg.txt</a> +</li> +<li>__get_CONTROL() +: <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">Ref_CoreReg.txt</a> +</li> +<li>__get_FAULTMASK() +: <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">Ref_CoreReg.txt</a> +</li> +<li>__get_FPSCR() +: <a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">Ref_CoreReg.txt</a> +</li> +<li>__get_IPSR() +: <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">Ref_CoreReg.txt</a> +</li> +<li>__get_MSP() +: <a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">Ref_CoreReg.txt</a> +</li> +<li>__get_PRIMASK() +: <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">Ref_CoreReg.txt</a> +</li> +<li>__get_PSP() +: <a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">Ref_CoreReg.txt</a> +</li> +<li>__get_xPSR() +: <a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">Ref_CoreReg.txt</a> +</li> +<li>__ISB() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">Ref_cmInstr.txt</a> +</li> +<li>__LDREXB() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">Ref_cmInstr.txt</a> +</li> +<li>__LDREXH() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">Ref_cmInstr.txt</a> +</li> +<li>__LDREXW() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">Ref_cmInstr.txt</a> +</li> +<li>__NOP() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">Ref_cmInstr.txt</a> +</li> +<li>__PKHBT() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">Ref_cm4_simd.txt</a> +</li> +<li>__PKHTB() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">Ref_cm4_simd.txt</a> +</li> +<li>__QADD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">Ref_cm4_simd.txt</a> +</li> +<li>__QADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">Ref_cm4_simd.txt</a> +</li> +<li>__QADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">Ref_cm4_simd.txt</a> +</li> +<li>__QASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">Ref_cm4_simd.txt</a> +</li> +<li>__QSAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">Ref_cm4_simd.txt</a> +</li> +<li>__QSUB() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">Ref_cm4_simd.txt</a> +</li> +<li>__QSUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5">Ref_cm4_simd.txt</a> +</li> +<li>__QSUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61">Ref_cm4_simd.txt</a> +</li> +<li>__RBIT() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">Ref_cmInstr.txt</a> +</li> +<li>__REV() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">Ref_cmInstr.txt</a> +</li> +<li>__REV16() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">Ref_cmInstr.txt</a> +</li> +<li>__REVSH() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">Ref_cmInstr.txt</a> +</li> +<li>__ROR() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">Ref_cmInstr.txt</a> +</li> +<li>__SADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984">Ref_cm4_simd.txt</a> +</li> +<li>__SADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac20aa0f741d0a1494d58c531e38d5785">Ref_cm4_simd.txt</a> +</li> +<li>__SASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a">Ref_cm4_simd.txt</a> +</li> +<li>__SEL() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe">Ref_cm4_simd.txt</a> +</li> +<li>__set_BASEPRI() +: <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">Ref_CoreReg.txt</a> +</li> +<li>__set_CONTROL() +: <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">Ref_CoreReg.txt</a> +</li> +<li>__set_FAULTMASK() +: <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">Ref_CoreReg.txt</a> +</li> +<li>__set_FPSCR() +: <a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">Ref_CoreReg.txt</a> +</li> +<li>__set_MSP() +: <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">Ref_CoreReg.txt</a> +</li> +<li>__set_PRIMASK() +: <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">Ref_CoreReg.txt</a> +</li> +<li>__set_PSP() +: <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">Ref_CoreReg.txt</a> +</li> +<li>__SEV() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">Ref_cmInstr.txt</a> +</li> +<li>__SHADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">Ref_cm4_simd.txt</a> +</li> +<li>__SHADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea">Ref_cm4_simd.txt</a> +</li> +<li>__SHASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">Ref_cm4_simd.txt</a> +</li> +<li>__SHSAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">Ref_cm4_simd.txt</a> +</li> +<li>__SHSUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">Ref_cm4_simd.txt</a> +</li> +<li>__SHSUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b">Ref_cm4_simd.txt</a> +</li> +<li>__SMLAD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354">Ref_cm4_simd.txt</a> +</li> +<li>__SMLADX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f">Ref_cm4_simd.txt</a> +</li> +<li>__SMLALD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146">Ref_cm4_simd.txt</a> +</li> +<li>__SMLALDX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">Ref_cm4_simd.txt</a> +</li> +<li>__SMLSD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">Ref_cm4_simd.txt</a> +</li> +<li>__SMLSDX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e">Ref_cm4_simd.txt</a> +</li> +<li>__SMLSLD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">Ref_cm4_simd.txt</a> +</li> +<li>__SMLSLDX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga83e69ef81057d3cbd06863d729385187">Ref_cm4_simd.txt</a> +</li> +<li>__SMUAD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257">Ref_cm4_simd.txt</a> +</li> +<li>__SMUADX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaee6390f86965cb662500f690b0012092">Ref_cm4_simd.txt</a> +</li> +<li>__SMUSD() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga039142a5368840683cf329cb55b73f84">Ref_cm4_simd.txt</a> +</li> +<li>__SMUSDX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">Ref_cm4_simd.txt</a> +</li> +<li>__SSAT() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">Ref_cmInstr.txt</a> +</li> +<li>__SSAT16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga95e666b82216066bf6064d1244e6883c">Ref_cm4_simd.txt</a> +</li> +<li>__SSAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">Ref_cm4_simd.txt</a> +</li> +<li>__SSUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">Ref_cm4_simd.txt</a> +</li> +<li>__SSUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">Ref_cm4_simd.txt</a> +</li> +<li>__STREXB() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">Ref_cmInstr.txt</a> +</li> +<li>__STREXH() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">Ref_cmInstr.txt</a> +</li> +<li>__STREXW() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">Ref_cmInstr.txt</a> +</li> +<li>__SXTAB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac540b4fc41d30778ba102d2a65db5589">Ref_cm4_simd.txt</a> +</li> +<li>__SXTB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a> +</li> +<li>__UADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">Ref_cm4_simd.txt</a> +</li> +<li>__UADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab3d7fd00d113b20fb3741a17394da762">Ref_cm4_simd.txt</a> +</li> +<li>__UASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga980353d2c72ebb879282e49f592fddc0">Ref_cm4_simd.txt</a> +</li> +<li>__UHADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabd0b0e2da2e6364e176d051687702b86">Ref_cm4_simd.txt</a> +</li> +<li>__UHADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">Ref_cm4_simd.txt</a> +</li> +<li>__UHASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga028f0732b961fb6e5209326fb3855261">Ref_cm4_simd.txt</a> +</li> +<li>__UHSAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga09e129e6613329aab87c89f1108b7ed7">Ref_cm4_simd.txt</a> +</li> +<li>__UHSUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">Ref_cm4_simd.txt</a> +</li> +<li>__UHSUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga48a55df1c3e73923b73819d7c19b392d">Ref_cm4_simd.txt</a> +</li> +<li>__UQADD16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9e2cc5117e79578a08b25f1e89022966">Ref_cm4_simd.txt</a> +</li> +<li>__UQADD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafa9af218db3934a692fb06fa728d8031">Ref_cm4_simd.txt</a> +</li> +<li>__UQASX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">Ref_cm4_simd.txt</a> +</li> +<li>__UQSAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gadecfdfabc328d8939d49d996f2fd4482">Ref_cm4_simd.txt</a> +</li> +<li>__UQSUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5ec4e2e231d15e5c692233feb3806187">Ref_cm4_simd.txt</a> +</li> +<li>__UQSUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9736fe816aec74fe886e7fb949734eab">Ref_cm4_simd.txt</a> +</li> +<li>__USAD8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac8855c07044239ea775c8128013204f0">Ref_cm4_simd.txt</a> +</li> +<li>__USADA8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">Ref_cm4_simd.txt</a> +</li> +<li>__USAT() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">Ref_cmInstr.txt</a> +</li> +<li>__USAT16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga967f516afff5900cf30f1a81907cdd89">Ref_cm4_simd.txt</a> +</li> +<li>__USAX() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e">Ref_cm4_simd.txt</a> +</li> +<li>__USUB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">Ref_cm4_simd.txt</a> +</li> +<li>__USUB8() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">Ref_cm4_simd.txt</a> +</li> +<li>__UXTAB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09">Ref_cm4_simd.txt</a> +</li> +<li>__UXTB16() +: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228">Ref_cm4_simd.txt</a> +</li> +<li>__WFE() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">Ref_cmInstr.txt</a> +</li> +<li>__WFI() +: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">Ref_cmInstr.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_b"></a>- b -</h3><ul> +<li>BusFault_IRQn +: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">Ref_NVIC.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_d"></a>- d -</h3><ul> +<li>DebugMonitor_IRQn +: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">Ref_NVIC.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_h"></a>- h -</h3><ul> +<li>HardFault_IRQn +: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">Ref_NVIC.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_i"></a>- i -</h3><ul> +<li>IRQn_Type +: <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">Ref_NVIC.txt</a> +</li> +<li>ITM_CheckChar() +: <a class="el" href="group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">Ref_Debug.txt</a> +</li> +<li>ITM_ReceiveChar() +: <a class="el" href="group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">Ref_Debug.txt</a> +</li> +<li>ITM_RxBuffer +: <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">Ref_Debug.txt</a> +</li> +<li>ITM_SendChar() +: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">Ref_Debug.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_m"></a>- m -</h3><ul> +<li>MemoryManagement_IRQn +: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">Ref_NVIC.txt</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_n"></a>- n -</h3><ul> +<li>NonMaskableInt_IRQn +: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">Ref_NVIC.txt</a> +</li> +<li>NVIC_ClearPendingIRQ() +: <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">Ref_NVIC.txt</a> +</li> +<li>NVIC_DecodePriority() +: <a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">Ref_NVIC.txt</a> +</li> +<li>NVIC_DisableIRQ() +: <a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">Ref_NVIC.txt</a> +</li> +<li>NVIC_EnableIRQ() +: <a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">Ref_NVIC.txt</a> +</li> +<li>NVIC_EncodePriority() +: <a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetActive() +: <a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPendingIRQ() +: <a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPriority() +: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPriorityGrouping() +: <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetPendingIRQ() +: <a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetPriority() +: <a class="el" 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Data can be transmitted via a certain global buffer variable towards the target system.</p> +<p>The Cortex-M3 / Cortex-M4 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that provides together with the <b>Serial Viewer Output (SVO)</b> trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:</p> +<ul> +<li><b>ITM Channel 0</b>: implements the <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function which can be used for printf-style output via the debug interface.</li> +</ul> +<ul> +<li><b>ITM Channel 31</b>: is reserved for the RTOS kernel and can be used for kernel awareness debugging.</li> +</ul> +<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul> +<li>ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.</li> +<li>The ITM channel 0 can be enabled for the user task.</li> +<li>ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.</li> +</ul> +</dd></dl> +<hr/> + <h2><a class="anchor" id="ITM_debug_uv"></a> +ITM Debug Support in uVision</h2> +<p>In a debug session, uVision uses the <b>Debug (printf) Viewer</b> window to display data.</p> +<p><b>Direction: Microcontroller --> uVision:</b></p> +<ul> +<li>Characters received via ITM communication channel 0 are written in a printf-style to the <b>Debug (printf) Viewer</b> window.</li> +</ul> +<p><b>Direction: uVision --> Microcontroller:</b></p> +<ul> +<li>Check if <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> variable is available (only performed once).</li> +<li>Read the character from the <b>Debug (printf) Viewer</b> window.</li> +<li>If <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> is empty, write character to <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>.</li> +</ul> +<dl class="note"><dt><b>Note:</b></dt><dd>The current solution does not use a buffer mechanism for transmitting the characters.</dd></dl> +<hr/> + <h2><a class="anchor" id="itm_debug_ex"></a> +Example:</h2> +<p>Example for the usage of the ITM Channel 31 for RTOS Kernels:</p> +<div class="fragment"><pre class="fragment"><span class="comment">// check if debugger connected and ITM channel enabled for tracing</span> +<span class="keywordflow">if</span> ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL >> 31))) { + + <span class="comment">// transmit trace data</span> + <span class="keywordflow">while</span> (ITM->PORT31_U32 == 0); + ITM->PORT[31].u8 = task_id; <span class="comment">// id of next task</span> + <span class="keywordflow">while</span> (ITM->PORT[31].u32 == 0); + ITM->PORT[31].u32 = task_status; <span class="comment">// status information</span> +} +</pre></div> <hr/><h2>Variable Documentation</h2> +<a class="anchor" id="ga12e68e55a7badc271b948d6c7230b2a8"></a><!-- doxytag: member="Ref_Debug.txt::ITM_RxBuffer" ref="ga12e68e55a7badc271b948d6c7230b2a8" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile int32_t <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<hr/><h2>Function Documentation</h2> +<a class="anchor" id="ga7f9bbabd9756d1a7eafb2d9bf27e0535"></a><!-- doxytag: member="Ref_Debug.txt::ITM_CheckChar" ref="ga7f9bbabd9756d1a7eafb2d9bf27e0535" args="(void)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t ITM_CheckChar </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function reads the external variable <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> and checks whether a character is available or not.</p> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>=0 - No character available</li> +<li>=1 - Character available </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga37b8f41cae703b5ff6947e271065558c"></a><!-- doxytag: member="Ref_Debug.txt::ITM_ReceiveChar" ref="ga37b8f41cae703b5ff6947e271065558c" args="(void)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t ITM_ReceiveChar </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function inputs a character via the external variable <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>Received character</li> +<li>=1 - No character received </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaaa7c716331f74d644bf6bf25cd3392d1"></a><!-- doxytag: member="Ref_Debug.txt::ITM_SendChar" ref="gaaa7c716331f74d644bf6bf25cd3392d1" args="(uint32_t ch)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t ITM_SendChar </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ch</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ch</td><td>Character to transmit</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>Character to transmit </dd></dl> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. 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align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">__QADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating addition. <a href="#gaf2f5a9132dcfc6d01d34cd971c425713"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea">__SHADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed addition with halved results. <a href="#ga524575b442ea01aec10c762bf4d85fea"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab3d7fd00d113b20fb3741a17394da762">__UADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned addition. <a href="#gab3d7fd00d113b20fb3741a17394da762"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafa9af218db3934a692fb06fa728d8031">__UQADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating addition. <a href="#gafa9af218db3934a692fb06fa728d8031"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">__UHADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned addition with halved results. <a href="#ga3a14e5485e59bf0f23595b7c2a94eb0b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">__SSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit signed subtraction. <a href="#gaba63bb52e1e93fb527e26f3d474da12e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61">__QSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating subtract. <a href="#ga753493a65493880c28baa82c151a0d61"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b">__SHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed subtraction with halved results. <a href="#gac3ec7215b354d925a239f3b31df2b77b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">__USUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned subtract. <a href="#gacb7257dc3b8e9acbd0ef0e31ff87d4b8"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9736fe816aec74fe886e7fb949734eab">__UQSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating subtraction. <a href="#ga9736fe816aec74fe886e7fb949734eab"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga48a55df1c3e73923b73819d7c19b392d">__UHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned subtraction with halved results. <a href="#ga48a55df1c3e73923b73819d7c19b392d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed addition. <a href="#gad0bf46373a1c05aabf64517e84be5984"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">__QADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating addition. <a href="#gae83a53ec04b496304bed6d9fe8f7461b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition with halved results. <a href="#ga15d8899a173effb8ad8c7268da32b60e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">__UADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition. <a href="#gaa1160f0cf76d6aa292fbad54a1aa6b74"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9e2cc5117e79578a08b25f1e89022966">__UQADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition. <a href="#ga9e2cc5117e79578a08b25f1e89022966"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabd0b0e2da2e6364e176d051687702b86">__UHADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition with halved results. <a href="#gabd0b0e2da2e6364e176d051687702b86"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction. <a href="#ga4262f73be75efbac6b46ab7c71aa6cbc"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5">__QSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating subtract. <a href="#gad089605c16df9823a2c8aaa37777aae5"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">__SHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction with halved results. <a href="#ga31328467f0f91b8ff9ae9a01682ad3bf"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">__USUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract. <a href="#ga9f2b77e11fc4a77b26c36c423ed45b4e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5ec4e2e231d15e5c692233feb3806187">__UQSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction. <a href="#ga5ec4e2e231d15e5c692233feb3806187"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">__UHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction with halved results. <a href="#ga1f7545b8dc33bb97982731cb9d427a69"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a">__SASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit addition and subtraction with exchange. <a href="#ga5845084fd99c872e98cf5553d554de2a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit add and subtract with exchange. <a href="#ga87618799672e1511e33964bc71467eb3"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition and subtraction with halved results. <a href="#gae0a649035f67627464fd80e7218c89d5"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga980353d2c72ebb879282e49f592fddc0">__UASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition and subtraction with exchange. <a href="#ga980353d2c72ebb879282e49f592fddc0"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">__UQASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition and subtraction with exchange. <a href="#ga5eff3ae5eabcd73f3049996ca391becb"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga028f0732b961fb6e5209326fb3855261">__UHASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition and subtraction with halved results and exchange. <a href="#ga028f0732b961fb6e5209326fb3855261"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">__SSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction and addition with exchange. <a href="#ga9d3bc5c539f9bd50f7d59ffa37ac6a65"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit subtract and add with exchange. <a href="#gab41eb2b17512ab01d476fc9d5bd19520"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction and addition with halved results. <a href="#gafadbd89c36b5addcf1ca10dd392db3e9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e">__USAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract and add with exchange. <a href="#ga578a082747436772c482c96d7a58e45e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gadecfdfabc328d8939d49d996f2fd4482">__UQSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction and addition with exchange. <a href="#gadecfdfabc328d8939d49d996f2fd4482"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga09e129e6613329aab87c89f1108b7ed7">__UHSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction and addition with halved results and exchange. <a href="#ga09e129e6613329aab87c89f1108b7ed7"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac8855c07044239ea775c8128013204f0">__USAD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference. <a href="#gac8855c07044239ea775c8128013204f0"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">__USADA8</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. <a href="#gad032bd21f013c5d29f5fcb6b0f02bc3f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga95e666b82216066bf6064d1244e6883c">__SSAT16</a> (uint32_t val1, const uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturate. <a href="#ga95e666b82216066bf6064d1244e6883c"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga967f516afff5900cf30f1a81907cdd89">__USAT16</a> (uint32_t val1, const uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit unsigned saturate. <a href="#ga967f516afff5900cf30f1a81907cdd89"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228">__UXTB16</a> (uint32_t val)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and zero-extend to 16-bits. <a href="#gab41d713653b16f8d9fef44d14e397228"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09">__UXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Extracted 16-bit to 32-bit unsigned addition. <a href="#gad25ce96db0f17096bbd815f4817faf09"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">__SXTB16</a> (uint32_t val)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and sign extend each to 16-bits. <a href="#ga38dce3dd13ba212e80ec3cff4abeb11a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac540b4fc41d30778ba102d2a65db5589">__SXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual extracted 8-bit to 16-bit signed addition. <a href="#gac540b4fc41d30778ba102d2a65db5589"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply. <a href="#gae326e368a1624d2dfb4b97c626939257"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaee6390f86965cb662500f690b0012092">__SMUADX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply with exchange. <a href="#gaee6390f86965cb662500f690b0012092"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354">__SMLAD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with single 32-bit accumulator. <a href="#gae0c86f3298532183f3a29f5bb454d354"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f">__SMLADX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. <a href="#ga9c286d330f4fb29b256335add91eec9f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146">__SMLALD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with single 64-bit accumulator. <a href="#gad80e9b20c1736fd798f897362273a146"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">__SMLALDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange with single 64-bit accumulator. <a href="#gad1adad1b3f2667328cc0db6c6b4f41cf"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga039142a5368840683cf329cb55b73f84">__SMUSD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply returning difference. <a href="#ga039142a5368840683cf329cb55b73f84"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">__SMUSDX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange returning difference. <a href="#gabb5bcba694bf17b141c32e6a8474f60e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">__SMLSD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. <a href="#gaf4350af7f2030c36f43b2c104a9d16cd"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e">__SMLSDX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. <a href="#ga5290ce5564770ad124910d2583dc0a9e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">__SMLSLD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. <a href="#ga5611f7314e0c8f53da377918dfbf42ee"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga83e69ef81057d3cbd06863d729385187">__SMLSLDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. <a href="#ga83e69ef81057d3cbd06863d729385187"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe">__SEL</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Select bytes based on GE bits. <a href="#gaf5448e591fe49161b6759b48aecb08fe"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">__QADD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating add. <a href="#ga17b873f246c9f5e9355760ffef3dad4a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">__QSUB</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating subtract. <a href="#ga3ba259f8f05a36f7b88b469a71ffc096"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">__PKHBT</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[15:0] of <em>val1</em> with bits[31:16] of <em>val2</em> levitated with the <em>val3</em>. <a href="#gaefb8ebf3a54e197464da1ff69a44f4b5"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">__PKHTB</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[31:16] of <em>val1</em> with bits[15:0] of <em>val2</em> right-shifted with the <em>val3</em>. <a href="#gafd8fe4a6d87e947caa81a69ec36c1666"></a><br/></td></tr> +</table> +<hr/><a name="details" id="details"></a><h2>Description</h2> +<p><b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 cores</b> to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.</p> +<p><b>SIMD Features:</b></p> +<ul> +<li>Simultaneous computation of 2x16-bit or 4x8-bit operands</li> +<li>Fractional arithmetic</li> +<li>User definable saturation modes (arbitrary word-width)</li> +<li>Dual 16x16 multiply-add/subtract 32x32 fractional MAC</li> +<li>Simultaneous 8/16-bit select operations</li> +<li>Performance up to 3.2 GOPS at 800MHz</li> +<li>Performance is achieved with a "near zero" increase in power consumption on a typical implementation</li> +</ul> +<p><b>Examples:</b> </p> +<p><b>Addition:</b> Add two values using SIMD function</p> +<div class="fragment"><pre class="fragment">uint32_t add_halfwords(uint32_t val1, uint32_t val2) +{ + <span class="keywordflow">return</span> <a class="code" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984" title="GE setting dual 16-bit signed addition.">__SADD16</a>(val1, val2); +} +</pre></div><p><b>Subtraction:</b> Subtract two values using SIMD function</p> +<div class="fragment"><pre class="fragment">uint32_t sub_halfwords(uint32_t val1, uint32_t val2) +{ + <span class="keywordflow">return</span> <a class="code" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc" title="GE setting dual 16-bit signed subtraction.">__SSUB16</a>(val1, val2); +} +</pre></div><p><b>Multiplication:</b> Performing a multiplication using SIMD function</p> +<div class="fragment"><pre class="fragment">uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2) +{ + <span class="keywordflow">return</span> <a class="code" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257" title="Q setting sum of dual 16-bit signed multiply.">__SMUAD</a>(val1, val2); +} +</pre></div> <hr/><h2>Function Documentation</h2> +<a class="anchor" id="gaefb8ebf3a54e197464da1ff69a44f4b5"></a><!-- doxytag: member="Ref_cm4_simd.txt::__PKHBT" ref="gaefb8ebf3a54e197464da1ff69a44f4b5" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __PKHBT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands </td></tr> + <tr><td class="paramname">val3</td><td>value for left-shifting <em>val2</em>. Value range [0..31].</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the combination of halfwords.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + res[31:16] = val2[31:16]<<val3 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafd8fe4a6d87e947caa81a69ec36c1666"></a><!-- doxytag: member="Ref_cm4_simd.txt::__PKHTB" ref="gafd8fe4a6d87e947caa81a69ec36c1666" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __PKHTB </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>second 16-bit operands </td></tr> + <tr><td class="paramname">val2</td><td>first 16-bit operands </td></tr> + <tr><td class="paramname">val3</td><td>value for right-shifting <em>val2</em>. Value range [1..32].</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the combination of halfwords.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val2[15:0]>>val3 + res[31:16] = val1[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga17b873f246c9f5e9355760ffef3dad4a"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QADD" ref="ga17b873f246c9f5e9355760ffef3dad4a" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to obtain the saturating add of two integers.<br/> + The Q bit is set if the operation saturates.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first summand of the saturating add operation. </td></tr> + <tr><td class="paramname">val2</td><td>second summand of the saturating add operation.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the saturating addition of val1 and val2.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[31:0] = SAT(val1 + SAT(val2 * 2)) +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae83a53ec04b496304bed6d9fe8f7461b"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QADD16" ref="gae83a53ec04b496304bed6d9fe8f7461b" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the saturated addition of the low halfwords, in the low halfword of the return value. </li> +<li>the saturated addition of the high halfwords, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf2f5a9132dcfc6d01d34cd971c425713"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QADD8" ref="gaf2f5a9132dcfc6d01d34cd971c425713" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1. </p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the saturated addition of the first byte of each operand in the first byte of the return value. </li> +<li>the saturated addition of the second byte of each operand in the second byte of the return value. </li> +<li>the saturated addition of the third byte of each operand in the third byte of the return value. </li> +<li>the saturated addition of the fourth byte of each operand in the fourth byte of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga87618799672e1511e33964bc71467eb3"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QASX" ref="ga87618799672e1511e33964bc71467eb3" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab41eb2b17512ab01d476fc9d5bd19520"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QSAX" ref="gab41eb2b17512ab01d476fc9d5bd19520" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. </li> +<li>the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3ba259f8f05a36f7b88b469a71ffc096"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QSUB" ref="ga3ba259f8f05a36f7b88b469a71ffc096" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to obtain the saturating subtraction of two integers.<br/> + The Q bit is set if the operation saturates.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>minuend of the saturating subtraction operation. </td></tr> + <tr><td class="paramname">val2</td><td>subtrahend of the saturating subtraction operation.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the saturating subtraction of val1 and val2.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[31:0] = SAT(val1 - SAT(val2 * 2)) +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad089605c16df9823a2c8aaa37777aae5"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QSUB16" ref="gad089605c16df9823a2c8aaa37777aae5" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li> +<li>the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga753493a65493880c28baa82c151a0d61"></a><!-- doxytag: member="Ref_cm4_simd.txt::__QSUB8" ref="ga753493a65493880c28baa82c151a0d61" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad0bf46373a1c05aabf64517e84be5984"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SADD16" ref="gad0bf46373a1c05aabf64517e84be5984" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed integer additions.<br/> + The GE bits in the APSR are set according to the results of the additions.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfwords in the low halfword of the return value. </li> +<li>the addition of the high halfwords in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac20aa0f741d0a1494d58c531e38d5785"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SADD8" ref="gac20aa0f741d0a1494d58c531e38d5785" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. </p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the addition of the second bytes of each operand, in the second byte of the return value. </li> +<li>the addition of the third bytes of each operand, in the third byte of the return value. </li> +<li>the addition of the fourth bytes of each operand, in the fourth byte of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5845084fd99c872e98cf5553d554de2a"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SASX" ref="ga5845084fd99c872e98cf5553d554de2a" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/> + The GE bits in the APRS are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf5448e591fe49161b6759b48aecb08fe"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SEL" ref="gaf5448e591fe49161b6759b48aecb08fe" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SEL </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>four selectable 8-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>four selectable 8-bit values.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria: <ul> +<li>if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] </li> +<li>if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] </li> +<li>if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] </li> +<li>if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga15d8899a173effb8ad8c7268da32b60e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHADD16" ref="ga15d8899a173effb8ad8c7268da32b60e" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two signed 16-bit integer additions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the low halfwords, in the low halfword of the return value. </li> +<li>the halved addition of the high halfwords, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] >> 1 + res[31:16] = val1[31:16] + val2[31:16] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga524575b442ea01aec10c762bf4d85fea"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHADD8" ref="ga524575b442ea01aec10c762bf4d85fea" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four signed 8-bit integer additions, halving the results. </p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] >> 1 + res[15:8] = val1[15:8] + val2[15:8] >> 1 + res[23:16] = val1[23:16] + val2[23:16] >> 1 + res[31:24] = val1[31:24] + val2[31:24] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae0a649035f67627464fd80e7218c89d5"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHASX" ref="gae0a649035f67627464fd80e7218c89d5" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = (val1[15:0] - val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafadbd89c36b5addcf1ca10dd392db3e9"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHSAX" ref="gafadbd89c36b5addcf1ca10dd392db3e9" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = (val1[15:0] + val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga31328467f0f91b8ff9ae9a01682ad3bf"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHSUB16" ref="ga31328467f0f91b8ff9ae9a01682ad3bf" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two signed 16-bit integer subtractions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li> +<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] >> 1 + res[31:16] = val1[31:16] - val2[31:16] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac3ec7215b354d925a239f3b31df2b77b"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SHSUB8" ref="gac3ec7215b354d925a239f3b31df2b77b" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four signed 8-bit integer subtractions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] >> 1 + res[15:8] = val1[15:8] - val2[15:8] >> 1 + res[23:16] = val1[23:16] - val2[23:16] >> 1 + res[31:24] = val1[31:24] - val2[31:24] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae0c86f3298532183f3a29f5bb454d354"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLAD" ref="gae0c86f3298532183f3a29f5bb454d354" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLAD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the product of each multiplication added to the accumulate value, as a 32-bit integer.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 + p2 + val3[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9c286d330f4fb29b256335add91eec9f"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLADX" ref="ga9c286d330f4fb29b256335add91eec9f" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLADX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 + p2 + val3[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad80e9b20c1736fd798f897362273a146"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLALD" ref="gad80e9b20c1736fd798f897362273a146" args="(uint32_t val1, uint32_t val2, uint64_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t __SMLALD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the product of each multiplication added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + sum = p1 + p2 + val3[63:32][31:0] + res[63:32] = sum[63:32] + res[31:0] = sum[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad1adad1b3f2667328cc0db6c6b4f41cf"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLALDX" ref="gad1adad1b3f2667328cc0db6c6b4f41cf" args="(uint32_t val1, uint32_t val2, unsigned long long val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">unsigned long long __SMLALDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned long long </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the product of each multiplication added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + sum = p1 + p2 + val3[63:32][31:0] + res[63:32] = sum[63:32] + res[31:0] = sum[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf4350af7f2030c36f43b2c104a9d16cd"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLSD" ref="gaf4350af7f2030c36f43b2c104a9d16cd" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLSD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.<br/> + The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 - p2 + val3[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5290ce5564770ad124910d2583dc0a9e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLSDX" ref="ga5290ce5564770ad124910d2583dc0a9e" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLSDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 - p2 + val3[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5611f7314e0c8f53da377918dfbf42ee"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLSLD" ref="ga5611f7314e0c8f53da377918dfbf42ee" args="(uint32_t val1, uint32_t val2, uint64_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t __SMLSLD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[63:0] = p1 - p2 + val3[63:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga83e69ef81057d3cbd06863d729385187"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMLSLDX" ref="ga83e69ef81057d3cbd06863d729385187" args="(uint32_t val1, uint32_t val2, unsigned long long val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">unsigned long long __SMLSLDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned long long </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[63:0] = p1 - p2 + val3[63:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae326e368a1624d2dfb4b97c626939257"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMUAD" ref="gae326e368a1624d2dfb4b97c626939257" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUAD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, adding the products together.<br/> + The Q bit is set if the addition overflows.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the sum of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 + p2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaee6390f86965cb662500f690b0012092"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMUADX" ref="gaee6390f86965cb662500f690b0012092" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUADX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.<br/> + The Q bit is set if the addition overflows.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 + p2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga039142a5368840683cf329cb55b73f84"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMUSD" ref="ga039142a5368840683cf329cb55b73f84" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUSD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 - p2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gabb5bcba694bf17b141c32e6a8474f60e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SMUSDX" ref="gabb5bcba694bf17b141c32e6a8474f60e" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUSDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 - p2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga95e666b82216066bf6064d1244e6883c"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SSAT16" ref="ga95e666b82216066bf6064d1244e6883c" args="(uint32_t val1, const uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSAT16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to saturate two signed 16-bit values to a selected signed range.<br/> + The Q bit is set if either operation saturates.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>two signed 16-bit values to be saturated. </td></tr> + <tr><td class="paramname">val2</td><td>bit position for saturation, an integral constant expression in the range 1 to 16.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul> +<li>the signed saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li> +<li>the signed saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> Saturate halfwords in val1 to the <span class="keywordtype">signed</span> range specified by the bit position in val2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9d3bc5c539f9bd50f7d59ffa37ac6a65"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SSAX" ref="ga9d3bc5c539f9bd50f7d59ffa37ac6a65" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga4262f73be75efbac6b46ab7c71aa6cbc"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SSUB16" ref="ga4262f73be75efbac6b46ab7c71aa6cbc" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit signed integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands of each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands of each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <ul> +<li>res is the return value, then: </li> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaba63bb52e1e93fb527e26f3d474da12e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SSUB8" ref="gaba63bb52e1e93fb527e26f3d474da12e" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four 8-bit signed integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands of each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands of each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on </b></dt><dd>the results of the operation.</dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac540b4fc41d30778ba102d2a65db5589"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SXTAB16" ref="gac540b4fc41d30778ba102d2a65db5589" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SXTAB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>values added to the zero-extended to 16-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the addition of <em>val1</em> and <em>val2</em>, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + SignExtended(val2[7:0]) + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga38dce3dd13ba212e80ec3cff4abeb11a"></a><!-- doxytag: member="Ref_cm4_simd.txt::__SXTB16" ref="ga38dce3dd13ba212e80ec3cff4abeb11a" args="(uint32_t val)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SXTB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the 8-bit values sign-extended to 16-bit values. <ul> +<li>sign-extended value of val[7:0] in the low halfword of the return value. </li> +<li>sign-extended value of val[23:16] in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = SignExtended(val[7:0] + res[31:16] = SignExtended(val[23:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaa1160f0cf76d6aa292fbad54a1aa6b74"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UADD16" ref="gaa1160f0cf76d6aa292fbad54a1aa6b74" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit unsigned integer additions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands for each addition. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands for each addition.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfwords in each operand, in the low halfword of the return value. </li> +<li>the addition of the high halfwords in each operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 </li> +<li>if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab3d7fd00d113b20fb3741a17394da762"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UADD8" ref="gab3d7fd00d113b20fb3741a17394da762" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands for each addition. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands for each addition.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga980353d2c72ebb879282e49f592fddc0"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UASX" ref="ga980353d2c72ebb879282e49f592fddc0" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="user"><dt><b>If <em>res</em> is the return value, then:</b></dt><dd><ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gabd0b0e2da2e6364e176d051687702b86"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHADD16" ref="gabd0b0e2da2e6364e176d051687702b86" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer additions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the low halfwords in each operand, in the low halfword of the return value. </li> +<li>the halved addition of the high halfwords in each operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] >> 1 + res[31:16] = val1[31:16] + val2[31:16] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3a14e5485e59bf0f23595b7c2a94eb0b"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHADD8" ref="ga3a14e5485e59bf0f23595b7c2a94eb0b" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] >> 1 + res[15:8] = val1[15:8] + val2[15:8] >> 1 + res[23:16] = val1[23:16] + val2[23:16] >> 1 + res[31:24] = val1[31:24] + val2[31:24] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga028f0732b961fb6e5209326fb3855261"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHASX" ref="ga028f0732b961fb6e5209326fb3855261" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. </li> +<li>the halved addition of the high halfword in the first operand and the low halfword in the second operand.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = (val1[15:0] - val2[31:16]) >> 1 + res[31:16] = (val1[31:16] + val2[15:0] ) >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga09e129e6613329aab87c89f1108b7ed7"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHSAX" ref="ga09e129e6613329aab87c89f1108b7ed7" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = (val1[15:0] + val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga1f7545b8dc33bb97982731cb9d427a69"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHSUB16" ref="ga1f7545b8dc33bb97982731cb9d427a69" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] >> 1 + res[31:16] = val1[31:16] - val2[31:16] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga48a55df1c3e73923b73819d7c19b392d"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UHSUB8" ref="ga48a55df1c3e73923b73819d7c19b392d" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] >> 1 + res[15:8] = val1[15:8] - val2[15:8] >> 1 + res[23:16] = val1[23:16] - val2[23:16] >> 1 + res[31:24] = val1[31:24] - val2[31:24] >> 1 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9e2cc5117e79578a08b25f1e89022966"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQADD16" ref="ga9e2cc5117e79578a08b25f1e89022966" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafa9af218db3934a692fb06fa728d8031"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQADD8" ref="gafa9af218db3934a692fb06fa728d8031" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5eff3ae5eabcd73f3049996ca391becb"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQASX" ref="ga5eff3ae5eabcd73f3049996ca391becb" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gadecfdfabc328d8939d49d996f2fd4482"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQSAX" ref="gadecfdfabc328d8939d49d996f2fd4482" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5ec4e2e231d15e5c692233feb3806187"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQSUB16" ref="ga5ec4e2e231d15e5c692233feb3806187" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands for each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands for each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9736fe816aec74fe886e7fb949734eab"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UQSUB8" ref="ga9736fe816aec74fe886e7fb949734eab" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac8855c07044239ea775c8128013204f0"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USAD8" ref="gac8855c07044239ea775c8128013204f0" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>The sum is returned as a single unsigned integer.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> absdiff1 = val1[7:0] - val2[7:0] + absdiff2 = val1[15:8] - val2[15:8] + absdiff3 = val1[23:16] - val2[23:16] + absdiff4 = val1[31:24] - val2[31:24] + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad032bd21f013c5d29f5fcb6b0f02bc3f"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USADA8" ref="gad032bd21f013c5d29f5fcb6b0f02bc3f" args="(uint32_t val1, uint32_t val2, uint32_t val3)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USADA8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val3</td><td>accumulation value.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> absdiff1 = val1[7:0] - val2[7:0] + absdiff2 = val1[15:8] - val2[15:8] + absdiff3 = val1[23:16] - val2[23:16] + absdiff4 = val1[31:24] - val2[31:24] + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 + res[31:0] = sum[31:0] + val3[31:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga967f516afff5900cf30f1a81907cdd89"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USAT16" ref="ga967f516afff5900cf30f1a81907cdd89" args="(uint32_t val1, const uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAT16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to saturate two signed 16-bit values to a selected unsigned range.<br/> + The Q bit is set if either operation saturates.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>two 16-bit values that are to be saturated. </td></tr> + <tr><td class="paramname">val2</td><td>bit position for saturation, and must be an integral constant expression in the range 0 to 15.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the saturation of the two signed 16-bit values, as non-negative values. <ul> +<li>the saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li> +<li>the saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> Saturate halfwords in val1 to the <span class="keywordtype">unsigned</span> range specified by the bit position in val2 +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga578a082747436772c482c96d7a58e45e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USAX" ref="ga578a082747436772c482c96d7a58e45e" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9f2b77e11fc4a77b26c36c423ed45b4e"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USUB16" ref="ga9f2b77e11fc4a77b26c36c423ed45b4e" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform two 16-bit unsigned integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gacb7257dc3b8e9acbd0ef0e31ff87d4b8"></a><!-- doxytag: member="Ref_cm4_simd.txt::__USUB8" ref="gacb7257dc3b8e9acbd0ef0e31ff87d4b8" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b></b></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="user"><dt><b></b></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad25ce96db0f17096bbd815f4817faf09"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UXTAB16" ref="gad25ce96db0f17096bbd815f4817faf09" args="(uint32_t val1, uint32_t val2)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UXTAB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>value added to the zero-extended to 16-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the 8-bit values in <em>val2</em>, zero-extended to 16-bit values and added to <em>val1</em>.</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] +</pre></div> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab41d713653b16f8d9fef44d14e397228"></a><!-- doxytag: member="Ref_cm4_simd.txt::__UXTB16" ref="gab41d713653b16f8d9fef44d14e397228" args="(uint32_t val)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UXTB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>the 8-bit values zero-extended to 16-bit values. <ul> +<li>zero-extended value of val[7:0] in the low halfword of the return value. </li> +<li>zero-extended value of val[23:16] in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="user"><dt><b>Operation:</b></dt><dd><div class="fragment"><pre class="fragment"> res[15:0] = ZeroExtended(val[7:0] ) + res[31:16] = ZeroExtended(val[23:16]) +</pre></div> </dd></dl> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html new file mode 100644 index 0000000..ffde56f --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html @@ -0,0 +1,231 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Peripheral Access</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-CORE +  <span id="projectnumber">Version 3.01</span> + </div> + <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__peripheral__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Peripheral Access</div> </div> +</div> +<div class="contents"> + +<p>Describes naming conventions, requirements, and optional features for accessing peripherals. +<a href="#details">More...</a></p> +<p>Each peripheral provides a data type definition with a name that is composed of a prefix <b><<em>device abbreviation></em>_</b> and the <b><<em>peripheral name</em>>_</b>, for example <b>LPC_UART</b> for the device <b>LPC</b> and the peripheral <b>UART</b>. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example <b>LPC_UART0</b>, <b>LPC_UART1</b>.</p> +<ul> +<li>The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:<br/> + <div class="fragment"><pre class="fragment"><span class="preprocessor"> #define __I volatile const </span> +<span class="preprocessor"> #define __O volatile </span> +<span class="preprocessor"> #define __IO volatile </span> +</pre></div></li> +</ul> +<ul> +<li>The following typedef is an example for a UART. <<em>device abbreviation</em>>_UART_TypeDef: defines the generic register layout for all UART channels in a device. <br/> + <div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct</span> +{ + <span class="keyword">union </span>{ + __I uint8_t RBR; <span class="comment">/* Offset: 0x000 (R/ ) Receiver Buffer Register */</span> + __O uint8_t THR; <span class="comment">/* Offset: 0x000 ( /W) Transmit Holding Register */</span> + __IO uint8_t DLL; <span class="comment">/* Offset: 0x000 (R/W) Divisor Latch LSB */</span> + uint32_t RESERVED0; + }; + <span class="keyword">union </span>{ + __IO uint8_t DLM; <span class="comment">/* Offset: 0x004 (R/W) Divisor Latch MSB */</span> + __IO uint32_t IER; <span class="comment">/* Offset: 0x004 (R/W) Interrupt Enable Register */</span> + }; + <span class="keyword">union </span>{ + __I uint32_t IIR; <span class="comment">/* Offset: 0x008 (R/ ) Interrupt ID Register */</span> + __O uint8_t FCR; <span class="comment">/* Offset: 0x008 ( /W) FIFO Control Register */</span> + }; + __IO uint8_t LCR; <span class="comment">/* Offset: 0x00C (R/W) Line Control Register */</span> + uint8_t RESERVED1[7]; + __I uint8_t LSR; <span class="comment">/* Offset: 0x014 (R/ ) Line Status Register */</span> + uint8_t RESERVED2[7]; + __IO uint8_t SCR; <span class="comment">/* Offset: 0x01C (R/W) Scratch Pad Register */</span> + uint8_t RESERVED3[3]; + __IO uint32_t ACR; <span class="comment">/* Offset: 0x020 (R/W) Autobaud Control Register */</span> + __IO uint8_t ICR; <span class="comment">/* Offset: 0x024 (R/W) IrDA Control Register */</span> + uint8_t RESERVED4[3]; + __IO uint8_t FDR; <span class="comment">/* Offset: 0x028 (R/W) Fractional Divider Register */</span> + uint8_t RESERVED5[7]; + __IO uint8_t TER; <span class="comment">/* Offset: 0x030 (R/W) Transmit Enable Register */</span> + uint8_t RESERVED6[39]; + __I uint8_t FIFOLVL; <span class="comment">/* Offset: 0x058 (R/ ) FIFO Level Register */</span> +} LPC_UART_TypeDef; +</pre></div></li> +</ul> +<ul> +<li>To access the registers of the UART defined above, pointers to a register structure are defined. In this example <<em>device abbreviation</em>>_UART# are two pointers to UARTs defined with above register structure. <br/> + <div class="fragment"><pre class="fragment"><span class="preprocessor">#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )</span> +<span class="preprocessor">#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</span> +</pre></div></li> +</ul> +<ul> +<li>The registers in the various UARTs can now be referred in the user code as shown below:<br/> + <div class="fragment"><pre class="fragment">LPC_UART1->DR <span class="comment">// is the data register of UART1.</span> +</pre></div></li> +</ul> +<hr/> +<h2><a class="anchor" id="core_cmsis_pal_min_reqs"></a> +Minimal Requirements</h2> +<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/> +<br/> +</p> +<ul> +<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/> +<br/> + <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct</span> +{ + __IO uint32_t CTRL; <span class="comment">/* Offset: 0x000 (R/W) SysTick Control and Status Register */</span> + __IO uint32_t LOAD; <span class="comment">/* Offset: 0x004 (R/W) SysTick Reload Value Register */</span> + __IO uint32_t VAL; <span class="comment">/* Offset: 0x008 (R/W) SysTick Current Value Register */</span> + __I uint32_t CALIB; <span class="comment">/* Offset: 0x00C (R/ ) SysTick Calibration Register */</span> +} <a class="code" href="struct_sys_tick___type.html" title="Structure type to access the System Timer (SysTick).">SysTick_Type</a>; +</pre></div></li> +</ul> +<ul> +<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/> +<br/> + <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010) </span><span class="comment">/* SysTick Base Address */</span> +</pre></div></li> +</ul> +<ul> +<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/> +<br/> + <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE) </span><span class="comment">/* SysTick access definition */</span> +</pre></div></li> +</ul> +<p>These definitions allow accessing peripheral registers with simple assignments.</p> +<p><b>Example:</b> <br/> + </p> +<div class="fragment"><pre class="fragment">SysTick->CTRL = 0; +</pre></div><hr/> +<h2><a class="anchor" id="core_cmsis_pal_opts"></a> +Optional Features</h2> +<p>Optionally, the file <b><em>device</em>.h</b> may define:</p> +<ul> +<li>#define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>. It is recommended to use CAPITAL letters for such #define constants.</li> +</ul> +<ul> +<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>. </li> +</ul> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. 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searchResults.Nav(event,16)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_ctrl')">CTRL</a> + <div class="SRChildren"> + <a id="Item16_c0" onkeydown="return searchResults.NavChild(event,16,0)" onkeypress="return searchResults.NavChild(event,16,0)" onkeyup="return searchResults.NavChild(event,16,0)" class="SRScope" href="../struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f" target="_parent">SysTick_Type::CTRL()</a> + <a id="Item16_c1" onkeydown="return searchResults.NavChild(event,16,1)" onkeypress="return searchResults.NavChild(event,16,1)" onkeyup="return searchResults.NavChild(event,16,1)" class="SRScope" href="../struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328" target="_parent">MPU_Type::CTRL()</a> + <a id="Item16_c2" onkeydown="return searchResults.NavChild(event,16,2)" onkeypress="return searchResults.NavChild(event,16,2)" onkeyup="return searchResults.NavChild(event,16,2)" class="SRScope" href="../struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d" target="_parent">DWT_Type::CTRL()</a> + </div> + </div> +</div> +<div class="SRResult" id="SR_cyccnt"> + <div class="SREntry"> + <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4" target="_parent">CYCCNT</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_68.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_68.html new file mode 100644 index 0000000..db6d192 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_68.html @@ -0,0 +1,32 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_hardfault_5firqn"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85" target="_parent">HardFault_IRQn</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_hfsr"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d" target="_parent">HFSR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html new file mode 100644 index 0000000..f534a31 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html @@ -0,0 +1,124 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_n"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_n')">N</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0" target="_parent">APSR_Type::N()</a> + <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5" target="_parent">xPSR_Type::N()</a> + </div> + </div> +</div> +<div class="SRResult" id="SR_nonmaskableint_5firqn"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30" target="_parent">NonMaskableInt_IRQn</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_npriv"> + <div class="SREntry"> + <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605" target="_parent">nPRIV</a> + <span class="SRScope">CONTROL_Type</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fclearpendingirq"> + <div class="SREntry"> + <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" target="_parent">NVIC_ClearPendingIRQ</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fdecodepriority"> + <div class="SREntry"> + <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377" target="_parent">NVIC_DecodePriority</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fdisableirq"> + <div class="SREntry"> + <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" target="_parent">NVIC_DisableIRQ</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fenableirq"> + <div class="SREntry"> + <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" target="_parent">NVIC_EnableIRQ</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fencodepriority"> + <div class="SREntry"> + <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5" target="_parent">NVIC_EncodePriority</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fgetactive"> + <div class="SREntry"> + <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892" target="_parent">NVIC_GetActive</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fgetpendingirq"> + <div class="SREntry"> + <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662" target="_parent">NVIC_GetPendingIRQ</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fgetpriority"> + <div class="SREntry"> + <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" target="_parent">NVIC_GetPriority</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fgetprioritygrouping"> + <div class="SREntry"> + <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" target="_parent">NVIC_GetPriorityGrouping</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fsetpendingirq"> + <div class="SREntry"> + <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2" target="_parent">NVIC_SetPendingIRQ</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fsetpriority"> + <div class="SREntry"> + <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" target="_parent">NVIC_SetPriority</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fsetprioritygrouping"> + <div class="SREntry"> + <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354" target="_parent">NVIC_SetPriorityGrouping</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5fsystemreset"> + <div class="SREntry"> + <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46" target="_parent">NVIC_SystemReset</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_nvic_5ftype"> + <div class="SREntry"> + <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../struct_n_v_i_c___type.html" target="_parent">NVIC_Type</a> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6f.html new file mode 100644 index 0000000..e8d54e7 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6f.html @@ -0,0 +1,25 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_overview_2etxt"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../_overview_8txt.html" target="_parent">Overview.txt</a> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_72.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_72.html new file mode 100644 index 0000000..6bc5db5 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_72.html @@ -0,0 +1,198 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_rasr"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03" target="_parent">RASR</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rasr_5fa1"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185" target="_parent">RASR_A1</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rasr_5fa2"> + <div class="SREntry"> + <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014" target="_parent">RASR_A2</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rasr_5fa3"> + <div class="SREntry"> + <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d" target="_parent">RASR_A3</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rbar"> + <div class="SREntry"> + <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9" target="_parent">RBAR</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rbar_5fa1"> + <div class="SREntry"> + <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639" target="_parent">RBAR_A1</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rbar_5fa2"> + <div class="SREntry"> + <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395" target="_parent">RBAR_A2</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_rbar_5fa3"> + <div class="SREntry"> + <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804" target="_parent">RBAR_A3</a> + <span class="SRScope">MPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_ref_5fcm4_5fsimd_2etxt"> + <div class="SREntry"> + <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../_ref__cm4__simd_8txt.html" target="_parent">Ref_cm4_simd.txt</a> + </div> +</div> +<div class="SRResult" id="SR_ref_5fcminstr_2etxt"> + <div class="SREntry"> + <a id="Item9" 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class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_w"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_w')">w</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94" target="_parent">APSR_Type::w()</a> + <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879" target="_parent">IPSR_Type::w()</a> + <a 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src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_dwt_5ftype"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html" target="_parent">DWT_Type</a> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_64.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_64.html new file mode 100644 index 0000000..d7c6956 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_64.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_debugmonitor_5firqn"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" 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-0,0 +1,32 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_svcall_5firqn"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237" target="_parent">SVCall_IRQn</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRResult" id="SR_systick_5firqn"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7" target="_parent">SysTick_IRQn</a> + <span class="SRScope">Ref_NVIC.txt</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html new file mode 100644 index 0000000..748b4d8 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_wwdg_5fstm_5firqn"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2" target="_parent">WWDG_STM_IRQn</a> + <span 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class="SRResult" id="SR_ref_5fnvic_2etxt"> + <div class="SREntry"> + <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../_ref___n_v_i_c_8txt.html" target="_parent">Ref_NVIC.txt</a> + </div> +</div> +<div class="SRResult" id="SR_ref_5fperipheral_2etxt"> + <div class="SREntry"> + <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../_ref___peripheral_8txt.html" target="_parent">Ref_Peripheral.txt</a> + </div> +</div> +<div class="SRResult" id="SR_ref_5fsystemandclock_2etxt"> + <div class="SREntry"> + <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../_ref___system_and_clock_8txt.html" target="_parent">Ref_SystemAndClock.txt</a> + </div> +</div> +<div class="SRResult" id="SR_ref_5fsystick_2etxt"> + <div class="SREntry"> + <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../_ref___systick_8txt.html" target="_parent">Ref_Systick.txt</a> + </div> +</div> +<div class="SRResult" id="SR_regmap_5fcmsis2arm_5fdoc_2etxt"> + <div class="SREntry"> + <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../_reg_map___c_m_s_i_s2_a_r_m___doc_8txt.html" target="_parent">RegMap_CMSIS2ARM_Doc.txt</a> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_m.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_m.png Binary files differnew file mode 100644 index 0000000..b429a16 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_m.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_5f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_5f.html new file mode 100644 index 0000000..804c2d0 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_5f.html @@ -0,0 +1,31 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR__5freserved0"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR__5freserved0')">_reserved0</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728" target="_parent">APSR_Type::_reserved0()</a> + <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa" target="_parent">IPSR_Type::_reserved0()</a> + <a id="Item0_c2" onkeydown="return searchResults.NavChild(event,0,2)" onkeypress="return searchResults.NavChild(event,0,2)" onkeyup="return searchResults.NavChild(event,0,2)" class="SRScope" href="../unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5" target="_parent">xPSR_Type::_reserved0()</a> + <a id="Item0_c3" onkeydown="return searchResults.NavChild(event,0,3)" onkeypress="return searchResults.NavChild(event,0,3)" onkeyup="return searchResults.NavChild(event,0,3)" class="SRScope" href="../union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50" target="_parent">CONTROL_Type::_reserved0()</a> + </div> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html new file mode 100644 index 0000000..7127f12 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html @@ -0,0 +1,123 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_c"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_c')">C</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6" target="_parent">APSR_Type::C()</a> + <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d" target="_parent">xPSR_Type::C()</a> + </div> + </div> +</div> +<div class="SRResult" id="SR_calib"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238" target="_parent">CALIB</a> + <span class="SRScope">SysTick_Type</span> + </div> +</div> +<div class="SRResult" id="SR_ccr"> + <div class="SREntry"> + <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8" target="_parent">CCR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_cfsr"> + <div class="SREntry"> + <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4" target="_parent">CFSR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_claimclr"> + <div class="SREntry"> + <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad" target="_parent">CLAIMCLR</a> + <span class="SRScope">TPI_Type</span> + </div> +</div> +<div class="SRResult" id="SR_claimset"> + <div class="SREntry"> + <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84" target="_parent">CLAIMSET</a> + <span class="SRScope">TPI_Type</span> + </div> +</div> +<div class="SRResult" id="SR_comp0"> + <div class="SREntry"> + <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904" target="_parent">COMP0</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_comp1"> + <div class="SREntry"> + <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c" target="_parent">COMP1</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_comp2"> + <div class="SREntry"> + <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332" target="_parent">COMP2</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_comp3"> + <div class="SREntry"> + <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f" target="_parent">COMP3</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_cpacr"> + <div class="SREntry"> + <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85" target="_parent">CPACR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_cpicnt"> + <div class="SREntry"> + <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc" target="_parent">CPICNT</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_cpuid"> + <div class="SREntry"> + <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032" target="_parent">CPUID</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_cspsr"> + <div class="SREntry"> + <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a" target="_parent">CSPSR</a> + <span class="SRScope">TPI_Type</span> + </div> +</div> +<div class="SRResult" id="SR_ctrl"> + <div class="SREntry"> + <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_ctrl')">CTRL</a> + <div class="SRChildren"> + <a id="Item14_c0" onkeydown="return searchResults.NavChild(event,14,0)" onkeypress="return searchResults.NavChild(event,14,0)" onkeyup="return searchResults.NavChild(event,14,0)" class="SRScope" href="../struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f" target="_parent">SysTick_Type::CTRL()</a> + <a id="Item14_c1" onkeydown="return searchResults.NavChild(event,14,1)" onkeypress="return searchResults.NavChild(event,14,1)" onkeyup="return searchResults.NavChild(event,14,1)" class="SRScope" href="../struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328" target="_parent">MPU_Type::CTRL()</a> + <a id="Item14_c2" onkeydown="return searchResults.NavChild(event,14,2)" onkeypress="return searchResults.NavChild(event,14,2)" onkeyup="return searchResults.NavChild(event,14,2)" class="SRScope" href="../struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d" target="_parent">DWT_Type::CTRL()</a> + </div> + </div> +</div> +<div class="SRResult" id="SR_cyccnt"> + <div class="SREntry"> + <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4" target="_parent">CYCCNT</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html new file mode 100644 index 0000000..2f3ed3d --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html @@ -0,0 +1,68 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_mask0"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f" target="_parent">MASK0</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mask1"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef" target="_parent">MASK1</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mask2"> + <div class="SREntry"> + <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e" target="_parent">MASK2</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mask3"> + <div class="SREntry"> + <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba" target="_parent">MASK3</a> + <span class="SRScope">DWT_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mmfar"> + <div class="SREntry"> + <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd" target="_parent">MMFAR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mmfr"> + <div class="SREntry"> + <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976" target="_parent">MMFR</a> + <span class="SRScope">SCB_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mvfr0"> + <div class="SREntry"> + <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1" target="_parent">MVFR0</a> + <span class="SRScope">FPU_Type</span> + </div> +</div> +<div class="SRResult" id="SR_mvfr1"> + <div class="SREntry"> + <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d" target="_parent">MVFR1</a> + <span class="SRScope">FPU_Type</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html new file mode 100644 index 0000000..a802996 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html @@ -0,0 +1,35 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_n"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_n')">N</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0" target="_parent">APSR_Type::N()</a> + <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5" target="_parent">xPSR_Type::N()</a> + </div> + </div> +</div> +<div class="SRResult" id="SR_npriv"> + <div class="SREntry"> + <a id="Item1" onkeydown="return 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b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_71.html @@ -0,0 +1,29 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_q"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_q')">Q</a> + <div class="SRChildren"> + <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return 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initNavTree('struct_core_debug___type.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">CoreDebug_Type Struct Reference</div> </div> +</div> +<div class="contents"> +<!-- doxytag: class="CoreDebug_Type" --> +<p>Structure type to access the Core Debug Register (CoreDebug). +</p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">DHCSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register. <a href="#a25c14c022c73a725a1736e903431095d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__O uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">DCRSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register. <a href="#afefa84bce7497652353a1b76d405d983"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">DCRDR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register. <a href="#ab8f4bb076402b61f7be6308075a789c9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">DEMCR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. <a href="#a5cdd51dbe3ebb7041880714430edd52d"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="ab8f4bb076402b61f7be6308075a789c9"></a><!-- doxytag: member="CoreDebug_Type::DCRDR" ref="ab8f4bb076402b61f7be6308075a789c9" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">CoreDebug_Type::DCRDR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="afefa84bce7497652353a1b76d405d983"></a><!-- doxytag: member="CoreDebug_Type::DCRSR" ref="afefa84bce7497652353a1b76d405d983" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O uint32_t <a class="el" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">CoreDebug_Type::DCRSR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a5cdd51dbe3ebb7041880714430edd52d"></a><!-- doxytag: member="CoreDebug_Type::DEMCR" ref="a5cdd51dbe3ebb7041880714430edd52d" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">CoreDebug_Type::DEMCR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a25c14c022c73a725a1736e903431095d"></a><!-- doxytag: member="CoreDebug_Type::DHCSR" ref="a25c14c022c73a725a1736e903431095d" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" 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</div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('struct_i_t_m___type.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">ITM_Type Struct Reference</div> </div> +</div> +<div class="contents"> +<!-- doxytag: class="ITM_Type" --> +<p>Structure type to access the Instrumentation Trace Macrocell Register (ITM). +</p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" >union {</td></tr> +<tr><td class="memItemLeft" >   __O uint8_t   <a class="el" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">u8</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. <a href="#afb9840e1a9a8abc9e175ff4593bb06c2"></a><br/></td></tr> +<tr><td class="memItemLeft" >   __O uint16_t   <a class="el" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">u16</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. <a href="#a8ff70d74e2edac38f1b2222e8165f566"></a><br/></td></tr> +<tr><td class="memItemLeft" >   __O uint32_t   <a class="el" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">u32</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. <a href="#a173603927cc7e19b6c205ffb0fee3627"></a><br/></td></tr> +<tr><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46">PORT</a> [32]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 ( /W) ITM Stimulus Port Registers. <a href="#afe056e8c8f8c5519d9b47611fa3a4c46"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">RESERVED0</a> [864]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a2c5ae30385b5f370d023468ea9914c0e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">TER</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE00 (R/W) ITM Trace Enable Register. <a href="#a91a040e1b162e1128ac1e852b4a0e589"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">RESERVED1</a> [15]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#afffce5b93bbfedbaee85357d0b07ebce"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">TPR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE40 (R/W) ITM Trace Privilege Register. <a href="#a93b480aac6da620bbb611212186d47fa"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">RESERVED2</a> [15]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#af56b2f07bc6b42cd3e4d17e1b27cff7b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">TCR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE80 (R/W) ITM Trace Control Register. <a href="#a58f169e1aa40a9b8afb6296677c3bb45"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="afe056e8c8f8c5519d9b47611fa3a4c46"></a><!-- doxytag: member="ITM_Type::PORT" ref="afe056e8c8f8c5519d9b47611fa3a4c46" args="[32]" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O { ... } <a class="el" href="struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46">ITM_Type::PORT</a>[32]</td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2c5ae30385b5f370d023468ea9914c0e"></a><!-- doxytag: member="ITM_Type::RESERVED0" ref="a2c5ae30385b5f370d023468ea9914c0e" args="[864]" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">ITM_Type::RESERVED0</a>[864]</td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="afffce5b93bbfedbaee85357d0b07ebce"></a><!-- doxytag: member="ITM_Type::RESERVED1" ref="afffce5b93bbfedbaee85357d0b07ebce" args="[15]" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">ITM_Type::RESERVED1</a>[15]</td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="af56b2f07bc6b42cd3e4d17e1b27cff7b"></a><!-- doxytag: member="ITM_Type::RESERVED2" ref="af56b2f07bc6b42cd3e4d17e1b27cff7b" args="[15]" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">ITM_Type::RESERVED2</a>[15]</td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a58f169e1aa40a9b8afb6296677c3bb45"></a><!-- doxytag: member="ITM_Type::TCR" ref="a58f169e1aa40a9b8afb6296677c3bb45" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">ITM_Type::TCR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a91a040e1b162e1128ac1e852b4a0e589"></a><!-- doxytag: member="ITM_Type::TER" ref="a91a040e1b162e1128ac1e852b4a0e589" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">ITM_Type::TER</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a93b480aac6da620bbb611212186d47fa"></a><!-- doxytag: member="ITM_Type::TPR" ref="a93b480aac6da620bbb611212186d47fa" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">ITM_Type::TPR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a12aa4eb4d9dcb589a5d953c836f4e8f4"></a><!-- doxytag: member="ITM_Type::u16" ref="a12aa4eb4d9dcb589a5d953c836f4e8f4" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O uint16_t <a class="el" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">ITM_Type::u16</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a6882fa5af67ef5c5dfb433b3b68939df"></a><!-- doxytag: member="ITM_Type::u32" ref="a6882fa5af67ef5c5dfb433b3b68939df" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O uint32_t <a class="el" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">ITM_Type::u32</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="abea77b06775d325e5f6f46203f582433"></a><!-- doxytag: member="ITM_Type::u8" ref="abea77b06775d325e5f6f46203f582433" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__O uint8_t <a class="el" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">ITM_Type::u8</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="struct_i_t_m___type.html">ITM_Type</a> </li> +<!-- window showing the filter options --> +<div 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All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html new file mode 100644 index 0000000..81f2d6f --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html @@ -0,0 +1,207 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>SysTick_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link 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id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div 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</div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('struct_sys_tick___type.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">SysTick_Type Struct Reference</div> </div> +</div> +<div class="contents"> +<!-- doxytag: class="SysTick_Type" --> +<p>Structure type to access the System Timer (SysTick). +</p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">CTRL</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) SysTick Control and Status Register. <a href="#af2ad94ac83e5d40fc6e34884bc1bec5f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">LOAD</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) SysTick Reload Value Register. <a href="#ae7bc9d3eac1147f3bba8d73a8395644f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">VAL</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) SysTick Current Value Register. <a href="#a0997ff20f11817f8246e8f0edac6f4e4"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">CALIB</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/ ) SysTick Calibration Register. <a href="#a9c9eda0ea6f6a7c904d2d75a6963e238"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="a9c9eda0ea6f6a7c904d2d75a6963e238"></a><!-- doxytag: member="SysTick_Type::CALIB" ref="a9c9eda0ea6f6a7c904d2d75a6963e238" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__I uint32_t <a class="el" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">SysTick_Type::CALIB</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="af2ad94ac83e5d40fc6e34884bc1bec5f"></a><!-- doxytag: member="SysTick_Type::CTRL" ref="af2ad94ac83e5d40fc6e34884bc1bec5f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">SysTick_Type::CTRL</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ae7bc9d3eac1147f3bba8d73a8395644f"></a><!-- doxytag: member="SysTick_Type::LOAD" ref="ae7bc9d3eac1147f3bba8d73a8395644f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">SysTick_Type::LOAD</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0997ff20f11817f8246e8f0edac6f4e4"></a><!-- doxytag: member="SysTick_Type::VAL" ref="a0997ff20f11817f8246e8f0edac6f4e4" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">SysTick_Type::VAL</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="struct_sys_tick___type.html">SysTick_Type</a> </li> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" 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name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" >struct {</td></tr> +<tr><td class="memItemLeft" >   uint32_t   <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">nPRIV</a>:1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Execution privilege in Thread mode <a href="#a666f4d16841194dd2ffb38cd9c1ff021"></a><br/></td></tr> +<tr><td class="memItemLeft" >   uint32_t   <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">SPSEL</a>:1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Stack to be used <a href="#ae452742bb12b77c4cae20418495334f1"></a><br/></td></tr> +<tr><td class="memItemLeft" >   uint32_t   <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">FPCA</a>:1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 FP extension active flag <a href="#a63fd27005fb7c3828f9f145a4fccf9a8"></a><br/></td></tr> +<tr><td class="memItemLeft" >   uint32_t   <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">_reserved0</a>:29</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">bit: 3..31 Reserved <a href="#ada408fafd29cbe29e0c71ef479bd7564"></a><br/></td></tr> +<tr><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">b</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#adc6a38ab2980d0e9577b5a871da14eb9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">w</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a6b642cca3d96da660b1198c133ca2a1f"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="af8c314273a1e4970a5671bd7f8184f50"></a><!-- doxytag: member="CONTROL_Type::_reserved0" ref="af8c314273a1e4970a5671bd7f8184f50" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type::_reserved0</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="adc6a38ab2980d0e9577b5a871da14eb9"></a><!-- doxytag: member="CONTROL_Type::b" ref="adc6a38ab2980d0e9577b5a871da14eb9" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">struct { ... } <a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type::b</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ac62cfff08e6f055e0101785bad7094cd"></a><!-- doxytag: member="CONTROL_Type::FPCA" ref="ac62cfff08e6f055e0101785bad7094cd" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type::FPCA</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a35c1732cf153b7b5c4bd321cf1de9605"></a><!-- doxytag: member="CONTROL_Type::nPRIV" ref="a35c1732cf153b7b5c4bd321cf1de9605" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type::nPRIV</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a8cc085fea1c50a8bd9adea63931ee8e2"></a><!-- doxytag: member="CONTROL_Type::SPSEL" ref="a8cc085fea1c50a8bd9adea63931ee8e2" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type::SPSEL</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a6b642cca3d96da660b1198c133ca2a1f"></a><!-- doxytag: member="CONTROL_Type::w" ref="a6b642cca3d96da660b1198c133ca2a1f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type::w</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a> </li> +<!-- window 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+} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; +} + +.memname { + white-space: nowrap; + font-weight: bold; + margin-left: 6px; +} + +.memproto { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 8px; + border-top-left-radius: 8px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug +{ + border-left:4px solid; + padding: 0 0 0 6px; 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j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2 + * + * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT (MIT-LICENSE.txt) + * and GPL (GPL-LICENSE.txt) licenses. + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * ui.core.js + */ +(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f<k.length;f++){var h=c.trim(k[f]),d="ui-resizable-"+h;var g=c('<div class="ui-resizable-handle '+d+'"></div>');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidth<k.width),l=a(k.height)&&h.maxHeight&&(h.maxHeight<k.height),g=a(k.width)&&h.minWidth&&(h.minWidth>k.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e<this._proportionallyResizeElements.length;e++){var g=this._proportionallyResizeElements[e];if(!this.borderDif){var d=[g.css("borderTopWidth"),g.css("borderRightWidth"),g.css("borderBottomWidth"),g.css("borderLeftWidth")],h=[g.css("paddingTop"),g.css("paddingRight"),g.css("paddingBottom"),g.css("paddingLeft")];this.borderDif=c.map(d,function(k,m){var l=parseInt(k,10)||0,n=parseInt(h[m],10)||0;return l+n})}if(c.browser.msie&&!(!(c(f).is(":hidden")||c(f).parents(":hidden").length))){continue}g.css({height:(f.height()-this.borderDif[0]-this.borderDif[2])||0,width:(f.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var e=this.element,h=this.options;this.elementOffset=e.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var 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a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_function_overview.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_function_overview.html new file mode 100644 index 0000000..d4b08b4 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_function_overview.html @@ -0,0 +1,217 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Function Overview</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-RTOS +  <span id="projectnumber">Version 1.00</span> + </div> + <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('_function_overview.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Function Overview </div> </div> +</div> +<div class="contents"> +<div class="textblock"><p>The following list provides a brief overview of all CMSIS-RTOS functions. Functions marked with $ are optional. A CMSIS RTOS implementation may not provided functions, but this is clearly indicated with <b>osFeatureXXXX</b> defines.</p> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html">Kernel Information and Control</a><ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a> : Start the RTOS kernel.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5">osKernelRunning</a> : Query if the RTOS kernel is running.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html">Thread Management</a><ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> : Start execution of a thread function.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a> : Stop execution of a thread function.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> : Pass execution to next ready thread function.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a> : Get the thread identifier to reference this thread.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">osThreadSetPriority</a> : Change the execution priority of a thread function.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9">osThreadGetPriority</a> : Obtain the current execution priority of a thread function.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html">Generic Wait Functions</a><ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> : Wait for a specified time.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> $ : Wait for any event of the type Signal, Message, or Mail.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html">Timer Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a> : Define attributes of the timer callback function.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">osTimerStart</a> : Start or restart the timer with a time value.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091">osTimerStop</a> : Stop the timer.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html">Signal Management</a><ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">osSignalSet</a> : Set signal flags of a thread.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8">osSignalClear</a> : Reset signal flags of a thread.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1">osSignalGet</a> : Read signal flags of a thread.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">osSignalWait</a> : Suspend execution until specific signal flags are set.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html">Mutex Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a> : Define and initialize a mutex.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a> : Obtain a mutex or Wait until it becomes available.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">osMutexRelease</a> : Release a mutex.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html">Semaphore Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">osSemaphoreCreate</a> : Define and initialize a semaphore.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">osSemaphoreWait</a> : Obtain a semaphore token or Wait until it becomes available.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">osSemaphoreRelease</a> : Release a semaphore token.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html">Memory Pool Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a> : Define and initialize a fix-size memory pool.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">osPoolAlloc</a> : Allocate a memory block.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">osPoolCAlloc</a> : Allocate a memory block and zero-set this block.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">osPoolFree</a> : Return a memory block to the memory pool.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html">Message Queue Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a> : Define and initialize a message queue.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">osMessagePut</a> : Put a message into a message queue.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">osMessageGet</a> : Get a message or suspend thread execution until message arrives.</li> +</ul> +</li> +</ul> +<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html">Mail Queue Management</a> $<ul> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a> : Define and initialize a mail queue with fix-size memory blocks.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">osMailAlloc</a> : Allocate a memory block.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">osMailCAlloc</a> : Allocate a memory block and zero-set this block.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">osMailPut</a> : Put a memory block into a mail queue.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">osMailGet</a> : Get a mail or suspend thread execution until mail arrives.</li> +<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">osMailFree</a> : Return a memory block to the mail queue. </li> +</ul> +</li> +</ul> +</div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return 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+<div class="header"> + <div class="summary"> +<a href="#nested-classes">Data Structures</a> | +<a href="#define-members">Defines</a> | +<a href="#typedef-members">Typedefs</a> | +<a href="#enum-members">Enumerations</a> | +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">cmsis_os.h File Reference</div> </div> +</div> +<div class="contents"> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_thread_def__t.html">osThreadDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Thread Definition structure contains startup information of a thread. <a href="structos_thread_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_timer_def__t.html">osTimerDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Timer Definition structure contains timer parameters. <a href="structos_timer_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Mutex Definition structure contains setup information for a mutex. <a href="structos_mutex_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Semaphore Definition structure contains setup information for a semaphore. <a href="structos_semaphore_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_pool_def__t.html">osPoolDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Definition structure for memory block allocation. <a href="structos_pool_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_message_q_def__t.html">osMessageQDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Definition structure for message queue. <a href="structos_message_q_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mail_q_def__t.html">osMailQDef_t</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Definition structure for mail queue. <a href="structos_mail_q_def__t.html#details">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Event structure contains detailed information about an event. <a href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">More...</a><br/></td></tr> +<tr><td colspan="2"><h2><a name="define-members"></a> +Defines</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1">osCMSIS</a>   0x00003</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">API version (main [31:16] .sub [15:0]) <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de">osCMSIS_KERNEL</a>   0x10000</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">RTOS identification and version (main [31:16] .sub [15:0]) <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289">osKernelSystemId</a>   "KERNEL V1.00"</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">RTOS identification string. <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">osFeature_MainThread</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">main thread 1=main can be thread, 0=not available <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">osFeature_Pool</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Memory Pools: 1=available, 0=not available. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Mail Queues: 1=available, 0=not available. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203">osFeature_MessageQ</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Message Queues: 1=available, 0=not available. <a href="group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6">osFeature_Signals</a>   8</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">maximum number of Signal Flags available per thread <a href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a">osFeature_Semaphore</a>   30</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">maximum count for SemaphoreInit function <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad">osFeature_Wait</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">osWait function: 1=available, 0=not available <a href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#a9eb9a7a797a42e4b55eb171ecc609ddb">osWaitForever</a>   0xFFFFFFFF</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Timeout value. <a href="#a9eb9a7a797a42e4b55eb171ecc609ddb"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f">osThreadDef</a>(name, priority, instances, stacksz)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a Thread Definition with function, priority, and stack requirements. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">osThread</a>(name)   &os_thread_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Thread defintion. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492">osTimerDef</a>(name, function)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Define a Timer object. <a href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678">osTimer</a>(name)   &os_timer_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Timer definition. <a href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3">osMutexDef</a>(name)   <a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> os_mutex_def_##name = { 0 }</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Define a Mutex. <a href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934">osMutex</a>(name)   &os_mutex_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Mutex defintion. <a href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b">osSemaphoreDef</a>(name)   <a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> os_semaphore_def_##name = { 0 }</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Define a Semaphore object. <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>(name)   &os_semaphore_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Semaphore definition. <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b">osPoolDef</a>(name, no, type)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Define a Memory Pool. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697">osPool</a>(name)   &os_pool_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Memory Pool definition. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326">osMessageQDef</a>(name, queue_sz, type)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a Message Queue Definition. <a href="group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97">osMessageQ</a>(name)   &os_messageQ_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Message Queue Definition. <a href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b">osMailQDef</a>(name, queue_sz, type)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a Mail Queue Definition. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2">osMailQ</a>(name)   &os_mailQ_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Mail Queue Definition. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2"></a><br/></td></tr> +<tr><td colspan="2"><h2><a name="typedef-members"></a> +Typedefs</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7">os_pthread</a> )(void const *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Entry point of a thread. <a href="#aee631e5ea1b700fc35695cc7bc574cf7"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065">os_ptimer</a> )(void const *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Entry point of a timer call back function. <a href="#aa2d85e49bde9f6951ff3545cd323f065"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_thread_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Thread ID identifies the thread (pointer to a thread control block). <a href="#adfeb153a84a81309e2d958268197617f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_timer_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Timer ID identifies the timer (pointer to a timer control block). <a href="#ab8530dd4273f1f5382187732e14fcaa7"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_mutex_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Mutex ID identifies the mutex (pointer to a mutex control block). <a href="#a3263c1ad9fd79b84f908d65e8da44ac2"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_semaphore_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Semaphore ID identifies the semaphore (pointer to a semaphore control block). <a href="#aa8968896c84094aa973683c84fa06f84"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_pool_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Pool ID identifies the memory pool (pointer to a memory pool control block). <a href="#a08d2e20fd9bbd96220fe068d420f3686"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_messageQ_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Message ID identifies the message queue (pointer to a message queue control block). <a href="#ad9ec70c32c6c521970636b521e12d17f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">typedef struct os_mailQ_cb * </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Mail ID identifies the mail queue (pointer to a mail queue control block). <a href="#a1dac049fb7725a8af8b26c71cbb373b5"></a><br/></td></tr> +<tr><td colspan="2"><h2><a name="enum-members"></a> +Enumerations</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#a7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> { <br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81">osPriorityIdle</a> = -3, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4">osPriorityLow</a> = -2, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6">osPriorityBelowNormal</a> = -1, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1">osPriorityNormal</a> = 0, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b">osPriorityAboveNormal</a> = +1, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2">osPriorityHigh</a> = +2, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af">osPriorityRealtime</a> = +3, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4">osPriorityError</a> = 0x84 +<br/> + }</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Priority used for thread control. <a href="cmsis__os_8h.html#a7f2b42f1983b9107775ec2a1c69a849a">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e">osStatus</a> { <br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f">osOK</a> = 0, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518">osEventSignal</a> = 0x08, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342">osEventMessage</a> = 0x10, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926">osEventMail</a> = 0x20, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177">osEventTimeout</a> = 0x40, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109">osErrorParameter</a> = 0x80, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d">osErrorResource</a> = 0x81, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467">osErrorTimeoutResource</a> = 0xC1, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f">osErrorISR</a> = 0x82, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65">osErrorISRRecursive</a> = 0x83, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f">osErrorPriority</a> = 0x84, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81">osErrorNoMemory</a> = 0x85, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee">osErrorValue</a> = 0x86, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc">osErrorOS</a> = 0xFF, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1">os_status_reserved</a> = 0x7FFFFFFF +<br/> + }</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Status code values returned by CMSIS-RTOS functions. <a href="cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e">More...</a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> { <br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951">osTimerOnce</a> = 0, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788">osTimerPeriodic</a> = 1 +<br/> + }</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Timer type value for the timer definition. <a href="cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9">More...</a><br/></td></tr> +<tr><td colspan="2"><h2><a name="func-members"></a> +Functions</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a> (<a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *thread_def, void *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Start the RTOS Kernel with executing the specified thread. <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5">osKernelRunning</a> (void)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Check if the RTOS kernel is already started. <a href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> (<a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *thread_def, void *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a thread and add it to Active Threads and set it to state READY. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a> (void)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Return the thread ID of the current running thread. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Terminate execution of a thread and remove it from Active Threads. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> (void)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Pass control to next thread that is in state <b>READY</b>. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">osThreadSetPriority</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> priority)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Change priority of an active thread. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9">osThreadGetPriority</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Get current priority of an active thread. <a href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> (uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for Timeout (Time Delay) <a href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> (uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for Signal, Message, Mail, or Timeout. <a href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a> (<a class="el" href="structos_timer_def__t.html">osTimerDef_t</a> *timer_def, <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> type, void *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a timer. <a href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">osTimerStart</a> (<a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> timer_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Start or restart a timer. <a href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091">osTimerStop</a> (<a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> timer_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Stop the timer. <a href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">osSignalSet</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, int32_t signal)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Set the specified Signal Flags of an active thread. <a href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8">osSignalClear</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, int32_t signal)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Clear the specified Signal Flags of an active thread. <a href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1">osSignalGet</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Get Signal Flags status of an active thread. <a href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">osSignalWait</a> (int32_t signals, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for one or more Signal Flags to become signaled for the current <b>RUNNING</b> thread. <a href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a> (<a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> *mutex_def)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create and Initialize a Mutex object. <a href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a> (<a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> mutex_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait until a Mutex becomes available. <a href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">osMutexRelease</a> (<a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> mutex_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Release a Mutex that was obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a>. <a href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">osSemaphoreCreate</a> (<a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> *semaphore_def, int32_t count)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create and Initialize a Semaphore object used for managing resources. <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">osSemaphoreWait</a> (<a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> semaphore_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait until a Semaphore token becomes available. <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">osSemaphoreRelease</a> (<a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> semaphore_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Release a Semaphore token. <a href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a> (<a class="el" href="structos_pool_def__t.html">osPoolDef_t</a> *pool_def)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create and Initialize a memory pool. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">osPoolAlloc</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a memory block from a memory pool. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">osPoolCAlloc</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a memory block from a memory pool and set memory block to zero. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">osPoolFree</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id, void *block)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Return an allocated memory block back to a specific memory pool. <a href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a> (<a class="el" href="structos_message_q_def__t.html">osMessageQDef_t</a> *queue_def, <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create and Initialize a Message Queue. <a href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">osMessagePut</a> (<a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> queue_id, uint32_t info, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Put a Message to a Queue. <a href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">osMessageGet</a> (<a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> queue_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a Message or Wait for a Message from a Queue. <a href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a> (<a class="el" href="structos_mail_q_def__t.html">osMailQDef_t</a> *queue_def, <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create and Initialize mail queue. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">osMailAlloc</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a memory block from a mail. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">osMailCAlloc</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a memory block from a mail and set memory block to zero. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">osMailPut</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, void *mail)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Put a mail to a queue. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">osMailGet</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a mail from a queue. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">osMailFree</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, void *mail)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Free a memory block from a mail. <a href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc"></a><br/></td></tr> +</table> +<hr/><h2>Define Documentation</h2> +<a class="anchor" id="a9eb9a7a797a42e4b55eb171ecc609ddb"></a><!-- doxytag: member="cmsis_os.h::osWaitForever" ref="a9eb9a7a797a42e4b55eb171ecc609ddb" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define osWaitForever   0xFFFFFFFF</td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osWaitForever</b> shall be consistent in every CMSIS-RTOS. wait forever timeout value </dd></dl> + +</div> +</div> +<hr/><h2>Typedef Documentation</h2> +<a class="anchor" id="aee631e5ea1b700fc35695cc7bc574cf7"></a><!-- doxytag: member="cmsis_os.h::os_pthread" ref="aee631e5ea1b700fc35695cc7bc574cf7" args=")(void const *argument)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef void(* <a class="el" href="cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7">os_pthread</a>)(void const *argument)</td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>os_pthread</b> shall be consistent in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="aa2d85e49bde9f6951ff3545cd323f065"></a><!-- doxytag: member="cmsis_os.h::os_ptimer" ref="aa2d85e49bde9f6951ff3545cd323f065" args=")(void const *argument)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef void(* <a class="el" href="cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065">os_ptimer</a>)(void const *argument)</td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>os_ptimer</b> shall be consistent in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="a1dac049fb7725a8af8b26c71cbb373b5"></a><!-- doxytag: member="cmsis_os.h::osMailQId" ref="a1dac049fb7725a8af8b26c71cbb373b5" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_mailQ_cb* <a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_mailQ_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="ad9ec70c32c6c521970636b521e12d17f"></a><!-- doxytag: member="cmsis_os.h::osMessageQId" ref="ad9ec70c32c6c521970636b521e12d17f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_messageQ_cb* <a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_messageQ_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="a3263c1ad9fd79b84f908d65e8da44ac2"></a><!-- doxytag: member="cmsis_os.h::osMutexId" ref="a3263c1ad9fd79b84f908d65e8da44ac2" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_mutex_cb* <a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_mutex_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="a08d2e20fd9bbd96220fe068d420f3686"></a><!-- doxytag: member="cmsis_os.h::osPoolId" ref="a08d2e20fd9bbd96220fe068d420f3686" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_pool_cb* <a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_pool_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="aa8968896c84094aa973683c84fa06f84"></a><!-- doxytag: member="cmsis_os.h::osSemaphoreId" ref="aa8968896c84094aa973683c84fa06f84" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_semaphore_cb* <a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_semaphore_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="adfeb153a84a81309e2d958268197617f"></a><!-- doxytag: member="cmsis_os.h::osThreadId" ref="adfeb153a84a81309e2d958268197617f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_thread_cb* <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_thread_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="ab8530dd4273f1f5382187732e14fcaa7"></a><!-- doxytag: member="cmsis_os.h::osTimerId" ref="ab8530dd4273f1f5382187732e14fcaa7" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">typedef struct os_timer_cb* <a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_timer_cb</b> is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<hr/><h2>Enumeration Type Documentation</h2> +<a class="anchor" id="adac860eb9e1b4b0619271e6595ed83d9"></a><!-- doxytag: member="cmsis_os.h::os_timer_type" ref="adac860eb9e1b4b0619271e6595ed83d9" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>os_timer_type</b> shall be consistent in every CMSIS-RTOS. </dd></dl> +<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0"> +<tr><td valign="top"><em><a class="anchor" id="gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951"></a><!-- doxytag: member="osTimerOnce" ref="gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951" args="" -->osTimerOnce</em> </td><td> +<p>one-shot timer </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788"></a><!-- doxytag: member="osTimerPeriodic" ref="gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788" args="" -->osTimerPeriodic</em> </td><td> +<p>repeating timer </p> +</td></tr> +</table> +</dd> +</dl> + +</div> +</div> +<a class="anchor" id="a7f2b42f1983b9107775ec2a1c69a849a"></a><!-- doxytag: member="cmsis_os.h::osPriority" ref="a7f2b42f1983b9107775ec2a1c69a849a" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPriority</b> shall be consistent in every CMSIS-RTOS. </dd></dl> +<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0"> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81"></a><!-- doxytag: member="osPriorityIdle" ref="ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81" args="" -->osPriorityIdle</em> </td><td> +<p>priority: idle (lowest) </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4"></a><!-- doxytag: member="osPriorityLow" ref="ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4" args="" -->osPriorityLow</em> </td><td> +<p>priority: low </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6"></a><!-- doxytag: member="osPriorityBelowNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6" args="" -->osPriorityBelowNormal</em> </td><td> +<p>priority: below normal </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1"></a><!-- doxytag: member="osPriorityNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1" args="" -->osPriorityNormal</em> </td><td> +<p>priority: normal (default) </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b"></a><!-- doxytag: member="osPriorityAboveNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b" args="" -->osPriorityAboveNormal</em> </td><td> +<p>priority: above normal </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2"></a><!-- doxytag: member="osPriorityHigh" ref="ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2" args="" -->osPriorityHigh</em> </td><td> +<p>priority: high </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af"></a><!-- doxytag: member="osPriorityRealtime" ref="ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af" args="" -->osPriorityRealtime</em> </td><td> +<p>priority: realtime (highest) </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4"></a><!-- doxytag: member="osPriorityError" ref="ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4" args="" -->osPriorityError</em> </td><td> +<p>system cannot determine priority or thread has illegal priority </p> +</td></tr> +</table> +</dd> +</dl> + +</div> +</div> +<a class="anchor" id="ae2e091fefc4c767117727bd5aba4d99e"></a><!-- doxytag: member="cmsis_os.h::osStatus" ref="ae2e091fefc4c767117727bd5aba4d99e" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osStatus</b> shall be consistent in every CMSIS-RTOS. </dd></dl> +<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0"> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f"></a><!-- doxytag: member="osOK" ref="gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f" args="" -->osOK</em> </td><td> +<p>function completed; no event occurred. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518"></a><!-- doxytag: member="osEventSignal" ref="gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518" args="" -->osEventSignal</em> </td><td> +<p>function completed; signal event occurred. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342"></a><!-- doxytag: member="osEventMessage" ref="gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342" args="" -->osEventMessage</em> </td><td> +<p>function completed; message event occurred. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926"></a><!-- doxytag: member="osEventMail" ref="gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926" args="" -->osEventMail</em> </td><td> +<p>function completed; mail event occurred. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177"></a><!-- doxytag: member="osEventTimeout" ref="gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177" args="" -->osEventTimeout</em> </td><td> +<p>function completed; timeout occurred. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109"></a><!-- doxytag: member="osErrorParameter" ref="gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109" args="" -->osErrorParameter</em> </td><td> +<p>parameter error: a mandatory parameter was missing or specified an incorrect object. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d"></a><!-- doxytag: member="osErrorResource" ref="gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d" args="" -->osErrorResource</em> </td><td> +<p>resource not available: a specified resource was not available. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467"></a><!-- doxytag: member="osErrorTimeoutResource" ref="gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467" args="" -->osErrorTimeoutResource</em> </td><td> +<p>resource not available within given time: a specified resource was not available within the timeout period. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f"></a><!-- doxytag: member="osErrorISR" ref="gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f" args="" -->osErrorISR</em> </td><td> +<p>not allowed in ISR context: the function cannot be called from interrupt service routines. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65"></a><!-- doxytag: member="osErrorISRRecursive" ref="gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65" args="" -->osErrorISRRecursive</em> </td><td> +<p>function called multiple times from ISR with same object. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f"></a><!-- doxytag: member="osErrorPriority" ref="gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f" args="" -->osErrorPriority</em> </td><td> +<p>system cannot determine priority or thread has illegal priority. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81"></a><!-- doxytag: member="osErrorNoMemory" ref="gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81" args="" -->osErrorNoMemory</em> </td><td> +<p>system is out of memory: it was impossible to allocate or reserve memory for the operation. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee"></a><!-- doxytag: member="osErrorValue" ref="gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee" args="" -->osErrorValue</em> </td><td> +<p>value of a parameter is out of range. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc"></a><!-- doxytag: member="osErrorOS" ref="gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc" args="" -->osErrorOS</em> </td><td> +<p>unspecified RTOS error: run-time error but no other error message fits. </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1"></a><!-- doxytag: member="os_status_reserved" ref="gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1" args="" -->os_status_reserved</em> </td><td> +<p>prevent from enum down-size compiler optimization. </p> +</td></tr> +</table> +</dd> +</dl> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="cmsis__os_8h.html">cmsis_os.h</a> </li> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Defines</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/doxygen.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/doxygen.png Binary files differnew file mode 100644 index 0000000..635ed52 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/doxygen.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/files.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/files.html new file mode 100644 index 0000000..87714d4 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/files.html @@ -0,0 +1,133 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Files</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-RTOS +  <span id="projectnumber">Version 1.00</span> + </div> + <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('files.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Files</div> </div> +</div> +<div class="contents"> +<div class="textblock">Here is a list of all files with brief descriptions:</div><table> + <tr><td class="indexkey"><a class="el" href="cmsis__os_8h.html">cmsis_os.h</a></td><td class="indexvalue"></td></tr> +</table> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Defines</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png Binary files differnew file mode 100644 index 0000000..3b7a29c --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png Binary files differnew file mode 100644 index 0000000..310e441 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png Binary files differnew file mode 100644 index 0000000..79aeaf7 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png Binary files differnew file mode 100644 index 0000000..1b703dd --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png Binary files differnew file mode 100644 index 0000000..ec51f17 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2node.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2node.png Binary files differnew file mode 100644 index 0000000..3b7a29c --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2node.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png Binary files differnew file mode 100644 index 0000000..f60a527 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/functions.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/functions.html new file mode 100644 index 0000000..4a29e5a --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/functions.html @@ -0,0 +1,201 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Data Fields</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-RTOS +  <span id="projectnumber">Version 1.00</span> + </div> + <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow2" class="tabs2"> + <ul class="tablist"> + <li><a href="annotated.html"><span>Data Structures</span></a></li> + <li><a href="classes.html"><span>Data Structure Index</span></a></li> + <li class="current"><a href="functions.html"><span>Data Fields</span></a></li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="functions.html"><span>All</span></a></li> + <li><a href="functions_vars.html"><span>Variables</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('functions.html',''); +</script> +<div id="doc-content"> +<div class="contents"> +<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div><ul> +<li>def +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6">osEvent</a> +</li> +<li>dummy +: <a class="el" href="structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca">osSemaphoreDef_t</a> +, <a class="el" href="structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca">osMutexDef_t</a> +</li> +<li>instances +: <a class="el" href="structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603">osThreadDef_t</a> +</li> +<li>item_sz +: <a class="el" href="structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">osMailQDef_t</a> +, <a class="el" href="structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">osMessageQDef_t</a> +, <a class="el" href="structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">osPoolDef_t</a> +</li> +<li>mail_id +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e">osEvent</a> +</li> +<li>message_id +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0">osEvent</a> +</li> +<li>p +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709">osEvent</a> +</li> +<li>pool +: <a class="el" href="structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">osPoolDef_t</a> +, <a class="el" href="structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">osMailQDef_t</a> +, <a class="el" href="structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">osMessageQDef_t</a> +</li> +<li>pool_sz +: <a class="el" href="structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763">osPoolDef_t</a> +</li> +<li>pthread +: <a class="el" href="structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e">osThreadDef_t</a> +</li> +<li>ptimer +: <a class="el" href="structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47">osTimerDef_t</a> +</li> +<li>queue_sz +: <a class="el" href="structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0">osMessageQDef_t</a> +, <a class="el" href="structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0">osMailQDef_t</a> +</li> +<li>signals +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6">osEvent</a> +</li> +<li>stacksize +: <a class="el" href="structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1">osThreadDef_t</a> +</li> +<li>status +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3">osEvent</a> +</li> +<li>tpriority +: <a class="el" href="structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7">osThreadDef_t</a> +</li> +<li>v +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc">osEvent</a> +</li> +<li>value +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f">osEvent</a> +</li> +</ul> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Defines</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals.html new file mode 100644 index 0000000..56b52f9 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals.html @@ -0,0 +1,442 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Index</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-RTOS +  <span id="projectnumber">Version 1.00</span> + </div> + <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="globals.html"><span>All</span></a></li> + <li><a href="globals_func.html"><span>Functions</span></a></li> + <li><a href="globals_type.html"><span>Typedefs</span></a></li> + <li><a href="globals_enum.html"><span>Enumerations</span></a></li> + <li><a href="globals_eval.html"><span>Enumerator</span></a></li> + <li><a href="globals_defs.html"><span>Defines</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li><a href="#index_o"><span>o</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('globals.html',''); +</script> +<div id="doc-content"> +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_o"></a>- o -</h3><ul> +<li>os_pthread +: <a class="el" href="cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7">cmsis_os.h</a> +</li> +<li>os_ptimer +: <a class="el" href="cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065">cmsis_os.h</a> +</li> +<li>os_status_reserved +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1">cmsis_os.h</a> +</li> +<li>os_timer_type +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">cmsis_os.txt</a> +, <a class="el" href="cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9">cmsis_os.h</a> +</li> +<li>osCMSIS +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1">cmsis_os.h</a> +</li> +<li>osCMSIS_KERNEL +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de">cmsis_os.h</a> +</li> +<li>osDelay() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">cmsis_os.h</a> +</li> +<li>osErrorISR +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f">cmsis_os.h</a> +</li> +<li>osErrorISRRecursive +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65">cmsis_os.h</a> +</li> +<li>osErrorNoMemory +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81">cmsis_os.h</a> +</li> +<li>osErrorOS +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc">cmsis_os.h</a> +</li> +<li>osErrorParameter +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109">cmsis_os.h</a> +</li> +<li>osErrorPriority +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f">cmsis_os.h</a> +</li> +<li>osErrorResource +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d">cmsis_os.h</a> +</li> +<li>osErrorTimeoutResource +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467">cmsis_os.h</a> +</li> +<li>osErrorValue +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee">cmsis_os.h</a> +</li> +<li>osEventMail +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926">cmsis_os.h</a> +</li> +<li>osEventMessage +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342">cmsis_os.h</a> +</li> +<li>osEventSignal +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518">cmsis_os.h</a> +</li> +<li>osEventTimeout +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177">cmsis_os.h</a> +</li> +<li>osFeature_MailQ +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">cmsis_os.h</a> +</li> +<li>osFeature_MainThread +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">cmsis_os.h</a> +</li> +<li>osFeature_MessageQ +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203">cmsis_os.h</a> +</li> +<li>osFeature_Pool +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">cmsis_os.h</a> +</li> +<li>osFeature_Semaphore +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a">cmsis_os.h</a> +</li> +<li>osFeature_Signals +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6">cmsis_os.h</a> +</li> +<li>osFeature_Wait +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad">cmsis_os.h</a> +</li> +<li>osKernelRunning() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5">cmsis_os.h</a> +</li> +<li>osKernelStart() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">cmsis_os.h</a> +</li> +<li>osKernelSystemId +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289">cmsis_os.h</a> +</li> +<li>osMailAlloc() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">cmsis_os.h</a> +</li> +<li>osMailCAlloc() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">cmsis_os.h</a> +</li> +<li>osMailCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">cmsis_os.h</a> +</li> +<li>osMailFree() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">cmsis_os.h</a> +</li> +<li>osMailGet() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">cmsis_os.h</a> +</li> +<li>osMailPut() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">cmsis_os.h</a> +</li> +<li>osMailQ +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2">cmsis_os.h</a> +</li> +<li>osMailQDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b">cmsis_os.h</a> +</li> +<li>osMailQId +: <a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">cmsis_os.h</a> +</li> +<li>osMessageCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">cmsis_os.h</a> +</li> +<li>osMessageGet() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">cmsis_os.h</a> +</li> +<li>osMessagePut() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">cmsis_os.h</a> +</li> +<li>osMessageQ +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97">cmsis_os.h</a> +</li> +<li>osMessageQDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326">cmsis_os.h</a> +</li> +<li>osMessageQId +: <a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">cmsis_os.h</a> +</li> +<li>osMutex +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934">cmsis_os.h</a> +</li> +<li>osMutexCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">cmsis_os.h</a> +</li> +<li>osMutexDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3">cmsis_os.h</a> +</li> +<li>osMutexId +: <a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">cmsis_os.h</a> +</li> +<li>osMutexRelease() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">cmsis_os.h</a> +</li> +<li>osMutexWait() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">cmsis_os.h</a> +</li> +<li>osOK +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f">cmsis_os.h</a> +</li> +<li>osPool +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697">cmsis_os.h</a> +</li> +<li>osPoolAlloc() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">cmsis_os.h</a> +</li> +<li>osPoolCAlloc() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">cmsis_os.h</a> +</li> +<li>osPoolCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">cmsis_os.h</a> +</li> +<li>osPoolDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b">cmsis_os.h</a> +</li> +<li>osPoolFree() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">cmsis_os.h</a> +</li> +<li>osPoolId +: <a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">cmsis_os.h</a> +</li> +<li>osPriority +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">cmsis_os.txt</a> +, <a class="el" href="cmsis__os_8h.html#a7f2b42f1983b9107775ec2a1c69a849a">cmsis_os.h</a> +</li> +<li>osPriorityAboveNormal +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b">cmsis_os.h</a> +</li> +<li>osPriorityBelowNormal +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6">cmsis_os.h</a> +</li> +<li>osPriorityError +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4">cmsis_os.h</a> +</li> +<li>osPriorityHigh +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2">cmsis_os.h</a> +</li> +<li>osPriorityIdle +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81">cmsis_os.h</a> +</li> +<li>osPriorityLow +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4">cmsis_os.h</a> +</li> +<li>osPriorityNormal +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1">cmsis_os.h</a> +</li> +<li>osPriorityRealtime +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af">cmsis_os.h</a> +</li> +<li>osSemaphore +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">cmsis_os.h</a> +</li> +<li>osSemaphoreCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">cmsis_os.h</a> +</li> +<li>osSemaphoreDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b">cmsis_os.h</a> +</li> +<li>osSemaphoreId +: <a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">cmsis_os.h</a> +</li> +<li>osSemaphoreRelease() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">cmsis_os.h</a> +</li> +<li>osSemaphoreWait() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">cmsis_os.h</a> +</li> +<li>osSignalClear() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8">cmsis_os.h</a> +</li> +<li>osSignalGet() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1">cmsis_os.h</a> +</li> +<li>osSignalSet() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">cmsis_os.h</a> +</li> +<li>osSignalWait() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">cmsis_os.h</a> +</li> +<li>osStatus +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">cmsis_os.txt</a> +, <a class="el" href="cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e">cmsis_os.h</a> +</li> +<li>osThread +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">cmsis_os.h</a> +</li> +<li>osThreadCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">cmsis_os.h</a> +</li> +<li>osThreadDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f">cmsis_os.h</a> +</li> +<li>osThreadGetId() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">cmsis_os.h</a> +</li> +<li>osThreadGetPriority() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9">cmsis_os.h</a> +</li> +<li>osThreadId +: <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">cmsis_os.h</a> +</li> +<li>osThreadSetPriority() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">cmsis_os.h</a> +</li> +<li>osThreadTerminate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">cmsis_os.h</a> +</li> +<li>osThreadYield() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">cmsis_os.h</a> +</li> +<li>osTimer +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678">cmsis_os.h</a> +</li> +<li>osTimerCreate() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">cmsis_os.h</a> +</li> +<li>osTimerDef +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492">cmsis_os.h</a> +</li> +<li>osTimerId +: <a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">cmsis_os.h</a> +</li> +<li>osTimerOnce +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951">cmsis_os.h</a> +</li> +<li>osTimerPeriodic +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788">cmsis_os.h</a> +</li> +<li>osTimerStart() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">cmsis_os.h</a> +</li> +<li>osTimerStop() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091">cmsis_os.h</a> +</li> +<li>osWait() +: <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">cmsis_os.h</a> +</li> +<li>osWaitForever +: <a class="el" href="cmsis__os_8h.html#a9eb9a7a797a42e4b55eb171ecc609ddb">cmsis_os.h</a> +</li> +</ul> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" 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+</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#define-members">Defines</a> | +<a href="#enum-members">Enumerations</a> | +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">Timer Management</div> </div> +<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div> +<div class="contents"> + +<p>Create and control timer and timer callback functions. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="define-members"></a> +Defines</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492">osTimerDef</a>(name, function)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Define a Timer object. <a href="#ga1c720627e08d1cc1afcad44e799ed492"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678">osTimer</a>(name)   &os_timer_def_##name</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Access a Timer definition. <a href="#ga1b8d670eaf964b2910fa06885e650678"></a><br/></td></tr> +<tr><td colspan="2"><h2><a name="enum-members"></a> +Enumerations</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> { <br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951">osTimerOnce</a> = 0, +<br/> +  <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788">osTimerPeriodic</a> = 1 +<br/> + }</td></tr> +<tr><td colspan="2"><h2><a name="func-members"></a> +Functions</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a> (<a class="el" href="structos_timer_def__t.html">osTimerDef_t</a> *timer_def, <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> type, void *argument)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Create a timer. <a href="#ga12cbe501cd7f1aec940cfeb4d8c73c89"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">osTimerStart</a> (<a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> timer_id, uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Start or restart a timer. <a href="#ga27a797a401b068e2644d1125f22a07ca"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091">osTimerStop</a> (<a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> timer_id)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Stop the timer. <a href="#ga58f36b121a812936435cacc6e1e0e091"></a><br/></td></tr> +</table> +<hr/><a name="details" id="details"></a><h2>Description</h2> +<p>The Timer Management function group allow creating and controlling of timers and callback functions in the system. A callback function is called when a time period expires whereby both one-shot and periodic timers are possible. A timer can be started, restarted, or stopped.</p> +<p>Timers are handled in the thread osTimerThread. Callback functions run under control of this thread and may use other CMSIS-RTOS API calls.</p> +<p>The figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the callback function.</p> +<div class="image"> +<img src="Timer.png" alt="Timer.png"/> +<div class="caption"> +Behavior of a Periodic Timer</div></div> +<hr/><h2>Define Documentation</h2> +<a class="anchor" id="ga1b8d670eaf964b2910fa06885e650678"></a><!-- doxytag: member="cmsis_os.h::osTimer" ref="ga1b8d670eaf964b2910fa06885e650678" args="(name)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define osTimer</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">name</td><td>)</td> + <td>   &os_timer_def_##name</td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>Access to the timer definition for the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a>.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">name</td><td>name of the timer object. </td></tr> + </table> + </dd> +</dl> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osTimer</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga1c720627e08d1cc1afcad44e799ed492"></a><!-- doxytag: member="cmsis_os.h::osTimerDef" ref="ga1c720627e08d1cc1afcad44e799ed492" args="(name, function)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define osTimerDef</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">name, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">function </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>Define the attributes of a timer.</p> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramname">name</td><td>name of the timer object. </td></tr> + <tr><td class="paramname">function</td><td>name of the timer call back function. </td></tr> + </table> + </dd> +</dl> +<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osTimerDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl> + +</div> +</div> +<hr/><h2>Enumeration Type Documentation</h2> +<a class="anchor" id="gadac860eb9e1b4b0619271e6595ed83d9"></a><!-- doxytag: member="cmsis_os.txt::os_timer_type" ref="gadac860eb9e1b4b0619271e6595ed83d9" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>os_timer_type</b> shall be consistent in every CMSIS-RTOS. The <a class="el" href="cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> specifies the a repeating (periodic) or one-shot timer for the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a>. </dd></dl> +<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0"> +<tr><td valign="top"><em><a class="anchor" id="gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951"></a><!-- doxytag: member="osTimerOnce" ref="gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951" args="" -->osTimerOnce</em> </td><td> +<p>one-shot timer </p> +</td></tr> +<tr><td valign="top"><em><a class="anchor" id="gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788"></a><!-- doxytag: member="osTimerPeriodic" ref="gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788" args="" -->osTimerPeriodic</em> </td><td> +<p>repeating timer </p> +</td></tr> +</table> +</dd> +</dl> + +</div> +</div> +<hr/><h2>Function Documentation</h2> +<a class="anchor" id="ga12cbe501cd7f1aec940cfeb4d8c73c89"></a><!-- doxytag: member="cmsis_os.h::osTimerCreate" ref="ga12cbe501cd7f1aec940cfeb4d8c73c89" args="(osTimerDef_t *timer_def, os_timer_type type, void *argument)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> osTimerCreate </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structos_timer_def__t.html">osTimerDef_t</a> * </td> + <td class="paramname"><em>timer_def</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> </td> + <td class="paramname"><em>type</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void * </td> + <td class="paramname"><em>argument</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timer_def</td><td>timer object referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678">osTimer</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">type</td><td>osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">argument</td><td>argument to the timer call back function. </td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>timer ID for reference by other functions or NULL in case of error. </dd></dl> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osTimerCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl> +<p>Create a one-shot or periodic timer and associate it with a callback function argument. The timer is in stopped until it is started with <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">osTimerStart</a>. </p> + +</div> +</div> +<a class="anchor" id="ga27a797a401b068e2644d1125f22a07ca"></a><!-- doxytag: member="cmsis_os.h::osTimerStart" ref="ga27a797a401b068e2644d1125f22a07ca" args="(osTimerId timer_id, uint32_t millisec)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osTimerStart </td> + <td>(</td> + <td class="paramtype"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> </td> + <td class="paramname"><em>timer_id</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>millisec</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timer_id</td><td>timer ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>time delay value of the timer. </td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osTimerStart</b> shall be consistent in every CMSIS-RTOS.</dd></dl> +<p>Start or restart the timer.</p> +<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/> +</p> +<ul> +<li><em>osOK:</em> the specified timer has been started or restarted.</li> +<li><em>osErrorParameter:</em> <em>timer_id</em> is incorrect. </li> +</ul> + +</div> +</div> +<a class="anchor" id="ga58f36b121a812936435cacc6e1e0e091"></a><!-- doxytag: member="cmsis_os.h::osTimerStop" ref="ga58f36b121a812936435cacc6e1e0e091" args="(osTimerId timer_id)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osTimerStop </td> + <td>(</td> + <td class="paramtype"><a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">osTimerId</a> </td> + <td class="paramname"><em>timer_id</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timer_id</td><td>timer ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osTimerStop</b> shall be consistent in every CMSIS-RTOS.</dd></dl> +<p>Stop the timer.</p> +<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/> +</p> +<ul> +<li><em>osOK:</em> the specified timer has been stopped.</li> +<li><em>osErrorParameter:</em> <em>timer_id</em> is incorrect.</li> +<li><em>osErrorResource:</em> the timer is not started. </li> +</ul> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return 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+</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#define-members">Defines</a> | +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">Generic Wait Functions</div> </div> +<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div> +<div class="contents"> + +<p>Wait for a time period or unspecified events. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="define-members"></a> +Defines</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad">osFeature_Wait</a>   1</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">osWait function: 1=available, 0=not available <a href="#ga6c97d38879ae86491628f6e647639bad"></a><br/></td></tr> +<tr><td colspan="2"><h2><a name="func-members"></a> +Functions</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> (uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for Timeout (Time Delay) <a href="#ga02e19d5e723bfb06ba9324d625162255"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> (uint32_t millisec)</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for Signal, Message, Mail, or Timeout. <a href="#gaad5030efe48c1ae9902502e73873bc70"></a><br/></td></tr> +</table> +<hr/><a name="details" id="details"></a><h2>Description</h2> +<p>The Generic Wait function group provides means for a time delay and allow to wait for unspecified events. </p> +<hr/><h2>Define Documentation</h2> +<a class="anchor" id="ga6c97d38879ae86491628f6e647639bad"></a><!-- doxytag: member="cmsis_os.h::osFeature_Wait" ref="ga6c97d38879ae86491628f6e647639bad" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define osFeature_Wait   1</td> + </tr> + </table> +</div> +<div class="memdoc"> +<p>A CMSIS-RTOS implementation may support the generic wait function <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a>. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad">osFeature_Wait</a> is 1 a generic wait function <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> is available. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad">osFeature_Wait</a> is 0 no generic wait function <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> is available. </p> + +</div> +</div> +<hr/><h2>Function Documentation</h2> +<a class="anchor" id="ga02e19d5e723bfb06ba9324d625162255"></a><!-- doxytag: member="cmsis_os.h::osDelay" ref="ga02e19d5e723bfb06ba9324d625162255" args="(uint32_t millisec)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osDelay </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>millisec</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>time delay value </td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function.</dd></dl> +<p>Wait for a specified time period in <em>millisec</em>.</p> +<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/> +</p> +<ul> +<li><em>osEventTimeout:</em> the time delay is executed.</li> +<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> cannot be called from interrupt service routines. </li> +</ul> + +</div> +</div> +<a class="anchor" id="gaad5030efe48c1ae9902502e73873bc70"></a><!-- doxytag: member="cmsis_os.h::osWait" ref="gaad5030efe48c1ae9902502e73873bc70" args="(uint32_t millisec)" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osWait </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>millisec</em></td><td>)</td> + <td></td> + </tr> + </table> +</div> +<div class="memdoc"> +<dl><dt><b>Parameters:</b></dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out </td></tr> + </table> + </dd> +</dl> +<dl class="return"><dt><b>Returns:</b></dt><dd>event that contains signal, message, or mail information or error code. </dd></dl> +<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osWait</b> shall be consistent in every CMSIS-RTOS.</dd></dl> +<p>Wait for any event of the type Signal, Message, Mail for a specified time period in <em>millisec</em>. When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an infinite time until a event occurs.</p> +<dl class="note"><dt><b>Note:</b></dt><dd>this function is optionally and may not be provided by all CMSIS-RTOS implementations.</dd></dl> +<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/> +</p> +<ul> +<li><em>osEventSignal:</em> a signal event occurred and is returned.</li> +<li><em>osEventMessage:</em> a message event occurred and is returned.</li> +<li><em>osEventMail:</em> a mail event occurred and is returned.</li> +<li><em>osEventTimeout:</em> the time delay is executed.</li> +<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> cannot be called from interrupt service routines. </li> +</ul> + +</div> +</div> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Defines</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + + + <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/installdox b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/installdox new file mode 100644 index 0000000..edf5bbf --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/installdox @@ -0,0 +1,112 @@ +#!/usr/bin/perl + +%subst = ( ); +$quiet = 0; + +while ( @ARGV ) { + $_ = shift @ARGV; + if ( s/^-// ) { + if ( /^l(.*)/ ) { + $v = ($1 eq "") ? shift @ARGV : $1; + ($v =~ /\/$/) || ($v .= "/"); + $_ = $v; + if ( /(.+)\@(.+)/ ) { + if ( exists $subst{$1} ) { + $subst{$1} = $2; + } else { + print STDERR "Unknown tag file $1 given with option -l\n"; + &usage(); + } + } else { + print STDERR "Argument $_ is invalid for option -l\n"; + &usage(); + } + } + elsif ( /^q/ ) { + $quiet = 1; + } + elsif ( /^\?|^h/ ) { + &usage(); + } + else { + print STDERR "Illegal option -$_\n"; + &usage(); + } + } + else { + push (@files, $_ ); + } +} + +foreach $sub (keys %subst) +{ + if ( $subst{$sub} eq "" ) + { + print STDERR "No substitute given for tag file `$sub'\n"; + &usage(); + } + elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" ) + { + print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; + } +} + +if ( ! @files ) { + if (opendir(D,".")) { + foreach $file ( readdir(D) ) { + $match = ".html"; + next if ( $file =~ /^\.\.?$/ ); + ($file =~ /$match/) && (push @files, $file); + ($file =~ /\.svg/) && (push @files, $file); + ($file =~ "navtree.js") && (push @files, $file); + } + closedir(D); + } +} + +if ( ! @files ) { + print STDERR "Warning: No input files given and none found!\n"; +} + +foreach $f (@files) +{ + if ( ! $quiet ) { + print "Editing: $f...\n"; + } + $oldf = $f; + $f .= ".bak"; + unless (rename $oldf,$f) { + print STDERR "Error: cannot rename file $oldf\n"; + exit 1; + } + if (open(F,"<$f")) { + unless (open(G,">$oldf")) { + print STDERR "Error: opening file $oldf for writing\n"; + exit 1; + } + if ($oldf ne "tree.js") { + while (<F>) { + s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g; + print G "$_"; + } + } + else { + while (<F>) { + s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g; + print G "$_"; + } + } + } + else { + print STDERR "Warning file $f does not exist\n"; + } + unlink $f; +} + +sub usage { + print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n"; + print STDERR "Options:\n"; + print STDERR " -l tagfile\@linkName tag file + URL or directory \n"; + print STDERR " -q Quiet mode\n\n"; + exit 1; +} diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/nav_f.png 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-0,0 +1,81 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).width(); + content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.height(); + var footerHeight = footer.height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); +} + + diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html new file mode 100644 index 0000000..68f4268 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html @@ -0,0 +1,32 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link 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class="SRScope">osEvent</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html new file mode 100644 index 0000000..72be715 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html @@ -0,0 +1,170 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> 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class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRResult" id="SR_ossemaphore"> + <div class="SREntry"> + <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac" target="_parent">osSemaphore</a> + <span class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRResult" id="SR_ossemaphoredef"> + <div class="SREntry"> + <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b" target="_parent">osSemaphoreDef</a> + <span class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRResult" id="SR_osthread"> + <div class="SREntry"> + <a id="Item20" onkeydown="return searchResults.Nav(event,20)" onkeypress="return searchResults.Nav(event,20)" onkeyup="return searchResults.Nav(event,20)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453" target="_parent">osThread</a> + <span class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRResult" id="SR_osthreaddef"> + <div class="SREntry"> + <a id="Item21" onkeydown="return searchResults.Nav(event,21)" onkeypress="return searchResults.Nav(event,21)" onkeyup="return searchResults.Nav(event,21)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f" target="_parent">osThreadDef</a> + <span class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRResult" id="SR_ostimer"> + <div class="SREntry"> + <a id="Item22" onkeydown="return searchResults.Nav(event,22)" onkeypress="return searchResults.Nav(event,22)" onkeyup="return searchResults.Nav(event,22)" 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class="SRScope">cmsis_os.h</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_r.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_r.png Binary files differnew file mode 100644 index 0000000..97ee8b4 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_r.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html new file mode 100644 index 0000000..17ea606 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html @@ -0,0 +1,35 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_def"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6" target="_parent">def</a> + <span class="SRScope">osEvent</span> + </div> +</div> +<div class="SRResult" id="SR_dummy"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_dummy')">dummy</a> + <div class="SRChildren"> + <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca" target="_parent">osMutexDef_t::dummy()</a> + <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca" target="_parent">osSemaphoreDef_t::dummy()</a> + </div> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html new file mode 100644 index 0000000..a924b79 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html @@ -0,0 +1,36 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_instances"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603" target="_parent">instances</a> + <span class="SRScope">osThreadDef_t</span> + </div> +</div> +<div class="SRResult" id="SR_item_5fsz"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_item_5fsz')">item_sz</a> + <div class="SRChildren"> + <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osPoolDef_t::item_sz()</a> + <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osMessageQDef_t::item_sz()</a> + <a id="Item1_c2" onkeydown="return searchResults.NavChild(event,1,2)" onkeypress="return searchResults.NavChild(event,1,2)" onkeyup="return searchResults.NavChild(event,1,2)" class="SRScope" href="../structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osMailQDef_t::item_sz()</a> + </div> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html new file mode 100644 index 0000000..bcddb85 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html @@ -0,0 +1,38 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_signals"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6" target="_parent">signals</a> + <span class="SRScope">osEvent</span> + </div> +</div> +<div class="SRResult" id="SR_stacksize"> + <div class="SREntry"> + <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1" target="_parent">stacksize</a> + <span class="SRScope">osThreadDef_t</span> + </div> +</div> +<div class="SRResult" id="SR_status"> + <div class="SREntry"> + <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3" target="_parent">status</a> + <span class="SRScope">osEvent</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html new file mode 100644 index 0000000..bd1c905 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRResult" id="SR_tpriority"> + <div class="SREntry"> + <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7" target="_parent">tpriority</a> + <span class="SRScope">osThreadDef_t</span> + </div> +</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html new file mode 100644 index 0000000..da6aade --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html @@ -0,0 +1,195 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>osPoolDef_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script 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class="contents"> +<!-- doxytag: class="osPoolDef_t" --> +<p>Definition structure for memory block allocation. + <a href="structos_pool_def__t.html#details">More...</a></p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763">pool_sz</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">number of items (elements) in the pool <a href="#ac112e786b2a234e0e45cb5bdbee53763"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">item_sz</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">size of an item <a href="#a4c2a0c691de3365c00ecd22d8102811f"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">pool</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">pointer to memory for pool <a href="#a269c3935f8bc66db70bccdd02cb05e3c"></a><br/></td></tr> +</table> +<hr/><a name="details" id="details"></a><h2>Description</h2> +<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_pool_def</b> is implementation specific in every CMSIS-RTOS. </dd></dl> +</div><hr/><h2>Field Documentation</h2> +<a class="anchor" id="a4c2a0c691de3365c00ecd22d8102811f"></a><!-- doxytag: member="osPoolDef_t::item_sz" ref="a4c2a0c691de3365c00ecd22d8102811f" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t <a class="el" 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index 0000000..310e441 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2link.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html new file mode 100644 index 0000000..ccc93af --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html @@ -0,0 +1,152 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>CPU Section (New)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__cpu_section__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">CPU Section (New)</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div> +<div class="contents"> +<p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.</p> +<pre> +<span class="opt"><cpu></span> + <span class="mand"><name><em>cpuNameType</em><name> + <revision><em>revisionType</em><revision> + <endian><em>endianType</em><endian> + <mpuPresent><em>xs:boolean</em><mpuPresent> + <fpuPresent><em>xs:boolean</em><fpuPresent> + <nvicPrioBits><em>scaledNonNegativeInteger</em><nvicPrioBits> + <vendorSystickConfig><em>xs:boolean</em><vendorSystickConfig></span> +<span class="opt"></cpu></span> +</pre><table class="cmtable" summary="CPU Section Elements"> +<tr> +<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>The predefined tokens are:<ul> +<li><span class="XML-Token">CM0</span>: ARM Cortex-M0</li> +<li><span class="XML-Token">CM0PLUS</span>: ARM Cortex-M0+</li> +<li><span class="XML-Token">CM3</span>: ARM Cortex-M3</li> +<li><span class="XML-Token">CM4</span>: ARM Cortex-M4</li> +<li><span class="XML-Token">SC000</span>: ARM Secure Core SC000</li> +<li><span class="XML-Token">SC300</span>: ARM Secure Core SC300</li> +<li><span class="XML-Token">other</span>: other processor architectures </li> +</ul> +</td><td>cpuNameType </td><td>1..1 </td></tr> +<tr> +<td>revisionType </td><td>Defines the HW revision of the processor. The defined version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 9]). </td><td>revisionType </td><td>1..1 </td></tr> +<tr> +<td>endian </td><td>Defines the endianess of the processor being one of:<ul> +<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li> +<li><span class="XML-Token">other</span>: the endianess is neither little nor big endian. </li> +</ul> +</td><td>endianType </td><td>1..1 </td></tr> +<tr> +<td>mpuPresent </td><td>Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>fpuPresent </td><td>Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>nvicPrioBits </td><td>Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr> +<td>vendorSystickConfig </td><td>Indicates whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the ARM defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +</table> +<h2><a class="anchor" id="cpuSection_ex"></a> +Example:</h2> +<div class="fragment"><pre class="fragment">... +<cpu> + <name>CM4</name> + <revision>r0p0</revision> + <endian>little</endian> + <mpuPresent><span class="keyword">true</span></mpuPresent> + <fpuPresent><span class="keyword">true</span></fpuPresent> + <nvicPrioBits>4</nvicPrioBits> + <vendorSystickConfig><span class="keyword">false</span></vendorSystickConfig> +</cpu> +... +</pre></div><p>This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. </p> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html new file mode 100644 index 0000000..b7d27f4 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html @@ -0,0 +1,154 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Extensions to the Device Section</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__device_section_extensions__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Extensions to the Device Section</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div> +<div class="contents"> +<p>A number of elements have been added to the device section. These elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.</p> +<pre> +<span class="mand"><b><device schemaVersion=<em>"xs:decimal"</em> xmlns:xs=<em>"http://www.w3.org/2001/XMLSchema-instance"</em> xs:noNamespaceSchemaLocation=<em>"CMSIS-SVD_Schema_1_1.xsd"</em>></b> + <span class="opt"><vendor><em>stringType</em></vendor> + <vendorID><em>stringType</em></vendorID></span> + <name><em>identifierType</em></name><span class="opt"> + <series><em>stringType</em></series></span> + <version><em>xs:string</em></version> + <description><em>xs:string</em></description><span class="opt"> + <licenseText><em>xs:string</em></licenseText> + <cpu><em>cpuType</em></cpu> + <headerSystemFilename><em>identifierType</em></headerSystemFilename> + <headerDefinitionsPrefix><em>identifierType</em></headerDefinitionsPrefix> +</span> + ... +<b></device></b> +</span> +</pre><table class="cmtable" summary="Device Section Extension Elements"> +<tr> +<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>vendor </td><td>This specifies the vendor of the device using the full name. </td><td>stringType </td><td>0..1 </td></tr> +<tr> +<td>vendorID </td><td>This specifies the vendor of the device using the vendor abbreviation that does not contain any spaces or special characters. This information shall be used for defining the directory. </td><td>stringType </td><td>0..1 </td></tr> +<tr> +<td>series </td><td>This element specifies the name of the device series. </td><td>stringType </td><td>0..1 </td></tr> +<tr> +<td>licenseText </td><td>The content of this tag will be copied into the header section of the generated device header file and shall contain the legal disclaimer. New lines can be inserted by using "\n". This section is mandatory if the SVD file shall be used for generating the device header file. </td><td>stringType </td><td>0..1 </td></tr> +<tr> +<td>headerSystemFilename </td><td>This tag specifies the file name (without extension) of the device-specific system include file (<code>system_<device>.h</code>; See CMSIS-Core description). This tag is used by the header file generator for customizing the include statement referencing the CMSIS system file within the CMSIS device header file. By default, the filename is "<kbd>system_<i>device:name</i>.h". In cases where a device series shares a single system header file, the name of the series shall be used instead of the individual device name. </td><td>identifierType </td><td>0..1 </td></tr> +<tr> +<td>headerDefinitionsPrefix </td><td>The element specifies the string being prepended to all type definition names generated in the CMSIS-Core device header file. This is used if the silicon vendor's software requires vendor-specific types in order to avoid name clashes with other definied types. </td><td>identifierType </td><td>0..1 </td></tr> +</table> +<h2><a class="anchor" id="deviceSectionExtensions_ex"></a> +Example:</h2> +<div class="fragment"><pre class="fragment">... +<device schemaVersion=<span class="stringliteral">"1.1"</span> xmlns:xs=<span class="stringliteral">"http://www.w3.org/2001/XMLSchema-instance"</span> xs:noNamespaceSchemaLocation=<span class="stringliteral">"CMSIS-SVD_Schema_1_1.xsd"</span>> + <vendor>Advanced RISC Machines</vendor> + <vendorID>ARM</vendorID> + ... + <series>ARMCM3</series> + ... + <licenseText> + ARM Limited (ARM) is supplying this software for use with Cortex-M \n + processor based microcontrollers. This file can be freely distributed \n + within development tools that are supporting such ARM based processors. \n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + </licenseText> + ... + <headerSystemFilename>system_ARMCM4</headeSystemFilename> + <headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix> + ... +</device> +... +</pre></div><p>This example describes a device from the vendor <b>Advanced RISC Machines</b> using <b>ARM</b> as short name. The device belongs to the device family identified by <b>ARMCM4</b>. The legal disclaimer in the header files generated from this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the generated device header file is named <b>system_ARMCM4.h</b> and all type definitions will be prepended with <b>ARM_</b>. </p> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html new file mode 100644 index 0000000..d66187a --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Element Groups</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__elem__type__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#groups">Modules</a> </div> + <div class="headertitle"> +<div class="title">Element Groups</div> </div> +</div> +<div class="contents"> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="groups"></a> +Modules</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dim_element_group__gr.html">dimElementGroup</a></td></tr> +<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__register_properties_group__gr.html">registerPropertiesGroup</a></td></tr> +</table> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html new file mode 100644 index 0000000..0908c1b --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html @@ -0,0 +1,197 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Enumerated Values Level</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__svd__xml__enum__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Enumerated Values Level</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></div></div> +<div class="contents"> +<div class="title">Enumerated Values</div><p> The concept of enumerated values creates a map between unsigned integers and an identifier string. In addition, a description string can be associated with each entry in the map.</p> +<pre> + 0 <-> disabled -> "the clock source clk0 is turned off" + 1 <-> enabled -> "the clock source clk1 is running" + </pre><p> This information is used for generating an <em>enum</em> in the device header file. The debugger may use this information to display the identifier string as well as the description. Just like symbolic constants making source code more readable, the system view in the debugger becomes more instructive. The detailed description can provide reference manual level details within the debugger.</p> +<hr/> +<pre> +<span class="mand"> +<b><enumeratedValues <span class="opt">derivedFrom</span>=<em>"xs:Name"</em>></b> +<span class="opt"> + <name><em>identifierType</em></name> + <usage><em>usageType</em></usage> +</span> + <enumeratedValue> + ... + </enumeratedValue> +<span class="opt"> + ... + <enumeratedValue> + ... + </enumeratedValue> +</span> +<b></enumeratedValues></b> +</span> +</pre><table class="cmtable" summary="Enumerated Values Level Schema"> +<tr> +<th>Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>derivedFrom </td><td>Makes a copy from a previously defined <em>enumeratedValues</em> section. No modifications are allowed. An <em>enumeratedValues</em> entry is referenced by its name. If the name is not unique throughout the description, it needs to be further qualified by specifying the associated field, register, and peripheral as required. For example: <pre> + field: clk.dis_en_enum + register + field: ctrl.clk.dis_en_enum + peripheral + register + field: timer0.ctrl.clk.dis_en_enum +</pre> </td><td>xs:Name </td><td>0..1 </td></tr> +<tr> +<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>Identifier for the whole enumeration section. </td><td>xs:Name </td><td>0..1 </td></tr> +<tr> +<td>usage </td><td>Possible values are <span class="XML-Token">read<em>,</em> write<em>, or</em> read-write</span>. This allows specifying two different enumerated values depending whether it is to be used for a read or a write access. If not specified, the default value <span class="XML-Token">read-write</span> is used. </td><td>enumUsageType </td><td>0..1 </td></tr> +<tr> +<td>enumeratedValue </td><td>Describes a single entry in the enumeration. The number of required items depends on the bit width of the associated field. See section below for details. </td><td nowrap="nowrap">  </td><td>1..* </td></tr> +</table> +<div class="title">Enumerated Value</div> <p>An <em>enumeratedValue</em> defines a map between an unsigned integer and a human readable string. <hr/> + <pre> +<span class="mand"> +<b><enumeratedValue></b></span></pre><pre><span class="mand"> <name><em>identifierType</em></name> + <span class="opt"><description><em>xs:string</em></description></span></span></pre><pre><span class="mand"> <choice> + <value><em>scaledNonNegativeInteger</em></value> + <isDefault><em>xs:boolean</em></isDefault> + </choice></span></pre><pre><span class="mand"><b></enumeratedValue></b> +</span> +</pre><table class="cmtable" summary="Enumerated Value"> +<tr> +<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>String describing the semantics of the value. Can be displayed instead of the value. </td><td>identifierType </td><td>0..1 </td></tr> +<tr> +<td>description </td><td>Extended string describing the value. </td><td>xs:string </td><td>0..1 </td></tr> +<tr class="choice"> +<td colspan="3"><em>choice of</em> </td><td>1..1 </td></tr> +<tr class="choice"> +<td align="right">value </td><td>Defines the constant of the bit-field that the name corresponds to. </td><td nowrap="nowrap">scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr class="choice"> +<td align="right">isDefault </td><td>Defines the name and description for all other values that are not listed explicitly. </td><td>xs:boolean </td><td>0..1 </td></tr> +</table> +<h2><a class="anchor" id="enum_ex2"></a> +Example:</h2> +<div class="fragment"><pre class="fragment"><enumeratedValues> + + <name>TimerIntSelect</name> + <usage>read-write</usage> + + <enumeratedValue> + <name>disabled</name> + <description>The clock source clk0 is turned off.</description> + <value>0</value> + </enumeratedValue> + + <enumeratedValue> + <name>reserved</name> + <description>Reserved values. Do not use.</description> + <isDefault><span class="keyword">true</span></isDefault> + </enumeratedValue> + +</enumeratedValues> +</pre></div> <div class="fragment"><pre class="fragment"><enumeratedValues> + + <name>TimerIntSelect</name> + <usage>read-write</usage> + + <enumeratedValue> + <name>disabled</name> + <description>Timer does not generate interrupts.</description> + <value>0</value> + </enumeratedValue> + + <enumeratedValue> + <name>enabled</name> + <description>Timer generates interrupts.</description> + <isDefault><span class="keyword">true</span></isDefault> + </enumeratedValue> + +</enumeratedValues> +</pre></div> </div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html new file mode 100644 index 0000000..40bf80f --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html @@ -0,0 +1,223 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Peripherals Level</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__svd__xml__peripherals__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Peripherals Level</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></div></div> +<div class="contents"> +<p>All peripherals of a device are enclosed within the tag <b><peripherals></b>. At least one peripheral has to be defined. Each peripheral is enclosed in the tag <b><peripheral></b>.</p> +<ul> +<li>Each peripheral describes all registers belonging to that peripheral.</li> +<li>The address range allocated by a peripheral is defined through one or more address blocks.</li> +<li>An address block and register addresses are specified relative to the base address of a peripheral. The address block information can be used for constructing a memory map for the device peripherals.</li> +</ul> +<dl class="remark"><dt><b>Remarks:</b></dt><dd>The memory map does not contain any information about RAM, ROM, or FLASH memory.</dd></dl> +<hr/> +<pre> +<span class="mand"> <b><peripherals></b> </span></pre><pre><span class="mand"> <b><peripheral</b> <span class="opt">derivedFrom</span>="<em>identifierType</em>"></span></pre><pre><span class="mand"> <name><em>identifierType</em></name> + <version><em>xs:string</em></version> + <description><em>xs:string</em></description> + <span class="opt"> + <groupName><em>identifierType</em></groupName> + <prependToName><em>identifierType</em></prependToName> + <appendToName><em>identifierType</em></appendToName> + <disableCondition><em>xs:string</em></disableCondition> + </span> + <baseAddress><em>scaledNonNegativeInteger</em></baseAddress> + <span class="opt"> + <em> <!-- registerPropertiesGroup --></em> + <size><em>scaledNonNegativeInteger</em></size> + <access><em>accessType</em></access> + <resetValue><em>scaledNonNegativeInteger</em></resetValue> + <resetMask><em>scaledNonNegativeInteger</em></resetMask> + <em> <!-- end of registerPropertiesGroup --></em> + </span> + <addressBlock> + <offset><em>scaledNonNegativeInteger</em></offset> + <size><em>scaledNonNegativeInteger</em></size> + <usage><em>usageType</em></usage> + </addressBlock><span class="opt"> + ... + <addressBlock><span class="mand"> + <offset><em>scaledNonNegativeInteger</em></offset> + <size><em>scaledNonNegativeInteger</em></size> + <usage><em>usageType</em></usage></span><span class="opt"> + </addressBlock></span> + <span class="opt"> + <interrupt></span><span class="mand"> + <name><em>identifierType</em></name> + <value><em>scaledNonNegativeInteger</em></value></span> + </interrupt></span></span></pre><pre><span class="mand"><span class="opt"> <registers> + ... + </registers></span></span></pre><pre><span class="mand"> <b></peripheral></b> + <span class="opt">... + <peripheral> + ... + </peripheral> + </span> +<b></peripherals></b> +</span> +</pre><table class="cmtable" summary="Peripheral Level Schema"> +<tr> +<th nowrap="nowrap">Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>derivedFrom </td><td>Specifies the name of a peripheral from which this peripheral will be derived. Values are inherit. Elements specified underneath will override inherited values. </td><td>xs:Name </td><td>0..1 </td></tr> +<tr> +<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>The name string is used to identify the peripheral. Peripheral names are required to be unique for a device. The name needs to be an ANSI C identifier to allow header file generation. </td><td>xs:Name </td><td>1..1 </td></tr> +<tr> +<td>version </td><td>The string specifies the version of this peripheral description. </td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>description </td><td>The string provides an overview of the purpose and functionality of the peripheral. </td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>groupName </td><td></td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>prependToName </td><td>All register names of this peripheral have their names prefixed with this string. </td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>appendToName </td><td>All register names of this peripheral have their names suffixed with this string. </td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>disableCondition </td><td>Is a C-language compliant logical expression returning a TRUE or FALSE result. If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed. <br/> + <br/> + Only constants and references to other registers contained in the description are allowed: <em><peripheral>-><register>-><field></em>, for example, (System->ClockControl->apbEnable == 0). The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |]. <dl class="attention"><dt><b>Attention:</b></dt><dd>Use this feature only in cases where accesses from the debugger to registers of un-clocked peripherals result in severe debugging failures. SVD is intended to provide static information and does not include any run-time computation or functions. Such capabilities can be added by the tools, and is beyond the scope of this description language. </dd></dl> +</td><td>xs:string </td><td>0..1 </td></tr> +<tr> +<td>baseAddress </td><td>Lowest address reserved or used by the peripheral. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr class="group1"> +<td colspan="4">See <a class="el" href="group__register_properties_group__gr.html">registerPropertiesGroup</a> for details. </td></tr> +<tr class="group1"> +<td align="right">size </td><td>Defines the default bit-width of any register contained in the device (implicit inheritance). </td><td>scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr class="group1"> +<td align="right">access </td><td>Defines the default access rights for all registers. </td><td>accessType </td><td>0..1 </td></tr> +<tr class="group1"> +<td align="right">resetValue </td><td>Defines the default value for all registers at RESET. </td><td>scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr class="group1"> +<td align="right">resetMask </td><td>Identifies which register bits have a defined reset value. </td><td>scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr class="group2"> +<td>addressBlock </td><td>Specifies an address range uniquely mapped to this peripheral. A peripheral must have at least one address block, but may allocate multiple distinct address ranges. If a peripheral is derived form another peripheral, the addressBlock is not mandatory. </td><td>addressBlockType </td><td>1..* </td></tr> +<tr class="group2"> +<td align="right">offset </td><td>Specifies the start address of an address block relative to the peripheral <em>baseAddress</em>. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr class="group2"> +<td align="right">size </td><td>Specifies the number of addressUnitBits being covered by this address block. The end address of an address block results from the sum of baseAddress, offset, and (size - 1). </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr class="group2"> +<td align="right">usage </td><td>The following predefined values can be used: <span class="XML-Token">registers<em>, </em> buffer<em>, or</em> reserved</span>. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr class="group1"> +<td>interrupt </td><td>A peripheral can have multiple associated interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers. </td><td>interruptType </td><td>0..* </td></tr> +<tr class="group1"> +<td align="right">name </td><td>The string represents the interrupt name. </td><td>XS:string </td><td>1..1 </td></tr> +<tr class="group1"> +<td align="right">value </td><td>Is the enumeration index value associated to the interrupt. </td><td>xs:integer </td><td>1..1 </td></tr> +<tr> +<td>registers </td><td>See <a class="el" href="group__svd__xml__registers__gr.html">Registers Level</a> for details. </td><td>  </td><td>0..1 </td></tr> +</table> +<h2><a class="anchor" id="periph_ex"></a> +Example:</h2> +<div class="fragment"><pre class="fragment">... +<peripheral> + <name>Timer0</name> + <version>1.0.32</version> + <description>Timer 0 is a simple 16 bit timer counting down ... </description> + <baseAddress>0x40000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>0x400</size> + <usage>registers</usage> + </addressBlock> + <interrupt><name>TIM0_INT</name><value>34</value></interrupt> + <registers> + ... + </registers> +</peripheral> + +<peripheral derivedFrom=<span class="stringliteral">"Timer0"</span>> + <name>Timer1</name> + <baseAddress>0x40000400</baseAddress> +</peripheral> +... +</pre></div> </div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. 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j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2 + * + * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT (MIT-LICENSE.txt) + * and GPL (GPL-LICENSE.txt) licenses. + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * ui.core.js + */ +(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f<k.length;f++){var h=c.trim(k[f]),d="ui-resizable-"+h;var g=c('<div class="ui-resizable-handle '+d+'"></div>');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidth<k.width),l=a(k.height)&&h.maxHeight&&(h.maxHeight<k.height),g=a(k.width)&&h.minWidth&&(h.minWidth>k.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e<this._proportionallyResizeElements.length;e++){var g=this._proportionallyResizeElements[e];if(!this.borderDif){var d=[g.css("borderTopWidth"),g.css("borderRightWidth"),g.css("borderBottomWidth"),g.css("borderLeftWidth")],h=[g.css("paddingTop"),g.css("paddingRight"),g.css("paddingBottom"),g.css("paddingLeft")];this.borderDif=c.map(d,function(k,m){var l=parseInt(k,10)||0,n=parseInt(h[m],10)||0;return l+n})}if(c.browser.msie&&!(!(c(f).is(":hidden")||c(f).parents(":hidden").length))){continue}g.css({height:(f.height()-this.borderDif[0]-this.borderDif[2])||0,width:(f.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var e=this.element,h=this.options;this.elementOffset=e.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var 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content="text/xhtml;charset=UTF-8"/> +<title>Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li class="current"><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('modules.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Reference</div> </div> +</div> +<div class="contents"> +<div class="textblock">Here is a list of all modules:</div><ul> +<li><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a><ul> +<li><a class="el" href="group__svd__xml__device__gr.html">Device Level</a></li> +<li><a class="el" href="group__svd__xml__peripherals__gr.html">Peripherals Level</a></li> +<li><a class="el" href="group__svd__xml__registers__gr.html">Registers Level</a></li> +<li><a class="el" href="group__svd__xml__fields__gr.html">Fields Level</a></li> +<li><a class="el" href="group__svd__xml__enum__gr.html">Enumerated Values Level</a></li> +</ul> +</li> +<li><a class="el" href="group__elem__type__gr.html">Element Groups</a><ul> +<li><a class="el" href="group__dim_element_group__gr.html">dimElementGroup</a></li> +<li><a class="el" href="group__register_properties_group__gr.html">registerPropertiesGroup</a></li> +</ul> +</li> +<li><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a><ul> +<li><a class="el" href="group__device_section_extensions__gr.html">Extensions to the Device Section</a></li> +<li><a class="el" href="group__cpu_section__gr.html">CPU Section (New)</a></li> +<li><a class="el" href="group__peripheral_section_extensions__gr.html">Extensions to the Peripheral Section</a></li> +<li><a class="el" href="group__cluster_level__gr.html">Cluster Level (New)</a></li> +<li><a class="el" href="group__register_section_extensions__gr.html">Extensions to the Register Section</a></li> +</ul> +</li> +<li><a class="el" href="group__schema__gr.html">CMSIS-SVD Schema File Ver. 1.0</a></li> +<li><a class="el" href="group__schema__1__1__gr.html">CMSIS-SVD Schema File Ver. 1.1 (draft)</a></li> +</ul> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. 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+ var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); +} + + diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html new file mode 100644 index 0000000..c81cae4 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html @@ -0,0 +1,833 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>SVD File Example</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('svd__example_pg.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">SVD File Example </div> </div> +</div> +<div class="contents"> +<div class="textblock"><div class="fragment"><pre class="fragment"><?xml version="1.0" encoding="utf-8"?> + +<!-- File naming: <vendor>_<part/series name>.svd --> + +<!-- + Copyright (C) 2012 ARM Limited. All rights reserved. + + Purpose: System Viewer Description (SVD) Example (Schema Version 1.0) + This is a description of a none-existent and incomplete device + for demonstration purposes only. + --> + +<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" > + <name>ARMCM3xxx</name> <!-- name of part or part series --> + <version>1.0</version> <!-- version of this description --> + <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description> + <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory --> + <width>32</width> <!-- bus width is 32 bits --> + <!-- default settings implicitly inherited by subsequent sections --> + <size>32</size> <!-- this is the default size (number of bits) of all peripherals + and register that do not define "size" themselves --> + <access>read-write</access> <!-- default access permission for all subsequent registers --> + <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset --> + <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used --> + + <peripherals> + <!-- Timer 0 --> + <peripheral> + <name>TIMER0</name> + <version>1.0</version> + <description>32 Timer / Counter, counting up or down from different sources</description> + <groupName>TIMER</groupName> + <baseAddress>0x40010000</baseAddress> + <size>32</size> + <access>read-write</access> + + <addressBlock> + <offset>0</offset> + <size>0x100</size> + <usage>registers</usage> + </addressBlock> + + <interrupt> + <name>TIMER0</name> + <value>0</value> + </interrupt> + + <registers> + <!-- CR: Control Register --> + <register> + <name>CR</name> + <description>Control Register</description> + <addressOffset>0x00</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0x1337F7F</resetMask> + + <fields> + <!-- EN: Enable --> + <field> + <name>EN</name> + <description>Enable</description> + <bitRange>[0:0]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Disable</name> + <description>Timer is disabled and does not operate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Enable</name> + <description>Timer is enabled and can operate</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- RST: Reset --> + <field> + <name>RST</name> + <description>Reset Timer</description> + <bitRange>[1:1]</bitRange> + <access>write-only</access> + <enumeratedValues> + <enumeratedValue> + <name>Reserved</name> + <description>Write as ZERO if necessary</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Reset_Timer</name> + <description>Reset the Timer</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- CNT: Counting Direction --> + <field> + <name>CNT</name> + <description>Counting direction</description> + <bitRange>[3:2]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Count_UP</name> + <description>Timer Counts UO and wraps, if no STOP condition is set</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Count_DOWN</name> + <description>Timer Counts DOWN and wraps, if no STOP condition is set</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>Toggle</name> + <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description> + <value>2</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- MODE: Operation Mode --> + <field> + <name>MODE</name> + <description>Operation Mode</description> + <bitRange>[6:4]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Continous</name> + <description>Timer runs continously</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Single_ZERO_MAX</name> + <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>Single_MATCH</name> + <description>Timer counts to the Value of MATCH Register and stops</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>Reload_ZERO_MAX</name> + <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description> + <value>3</value> + </enumeratedValue> + <enumeratedValue> + <name>Reload_MATCH</name> + <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description> + <value>4</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- PSC: Use Prescaler --> + <field> + <name>PSC</name> + <description>Use Prescaler</description> + <bitRange>[7:7]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Disabled</name> + <description>Prescaler is not used</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Enabled</name> + <description>Prescaler is used as divider</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- CNTSRC: Timer / Counter Soruce Divider --> + <field> + <name>CNTSRC</name> + <description>Timer / Counter Source Divider</description> + <bitRange>[11:8]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>CAP_SRC</name> + <description>Capture Source is used directly</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div2</name> + <description>Capture Source is divided by 2</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div4</name> + <description>Capture Source is divided by 4</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div8</name> + <description>Capture Source is divided by 8</description> + <value>3</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div16</name> + <description>Capture Source is divided by 16</description> + <value>4</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div32</name> + <description>Capture Source is divided by 32</description> + <value>5</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div64</name> + <description>Capture Source is divided by 64</description> + <value>6</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div128</name> + <description>Capture Source is divided by 128</description> + <value>7</value> + </enumeratedValue> + <enumeratedValue> + <name>CAP_SRC_div256</name> + <description>Capture Source is divided by 256</description> + <value>8</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- CAPSRC: Timer / COunter Capture Source --> + <field> + <name>CAPSRC</name> + <description>Timer / Counter Capture Source</description> + <bitRange>[15:12]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>CClk</name> + <description>Core Clock</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_0</name> + <description>GPIO A, PIN 0</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_1</name> + <description>GPIO A, PIN 1</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_2</name> + <description>GPIO A, PIN 2</description> + <value>3</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_3</name> + <description>GPIO A, PIN 3</description> + <value>4</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_4</name> + <description>GPIO A, PIN 4</description> + <value>5</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_5</name> + <description>GPIO A, PIN 5</description> + <value>6</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_6</name> + <description>GPIO A, PIN 6</description> + <value>7</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOA_7</name> + <description>GPIO A, PIN 7</description> + <value>8</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOB_0</name> + <description>GPIO B, PIN 0</description> + <value>9</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOB_1</name> + <description>GPIO B, PIN 1</description> + <value>10</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOB_2</name> + <description>GPIO B, PIN 2</description> + <value>11</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOB_3</name> + <description>GPIO B, PIN 3</description> + <value>12</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOC_0</name> + <description>GPIO C, PIN 0</description> + <value>13</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOC_5</name> + <description>GPIO C, PIN 1</description> + <value>14</value> + </enumeratedValue> + <enumeratedValue> + <name>GPIOC_6</name> + <description>GPIO C, PIN 2</description> + <value>15</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- CAPEDGE: Capture Edge --> + <field> + <name>CAPEDGE</name> + <description>Capture Edge, select which Edge should result in a counter increment or decrement</description> + <bitRange>[17:16]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>RISING</name> + <description>Only rising edges result in a counter increment or decrement</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>FALLING</name> + <description>Only falling edges result in a counter increment or decrement</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>BOTH</name> + <description>Rising and falling edges result in a counter increment or decrement</description> + <value>2</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- TRGEXT: Triggers an other Peripheral --> + <field> + <name>TRGEXT</name> + <description>Triggers an other Peripheral</description> + <bitRange>[21:20]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NONE</name> + <description>No Trigger is emitted</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DMA1</name> + <description>DMA Controller 1 is triggered, dependant on MODE</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>DMA2</name> + <description>DMA Controller 2 is triggered, dependant on MODE</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>UART</name> + <description>UART is triggered, dependant on MODE</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- Reload: Selects Reload Register n --> + <field> + <name>RELOAD</name> + <description>Select RELOAD Register n to reload Timer on condition</description> + <bitRange>[25:24]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>RELOAD0</name> + <description>Selects Reload Register number 0</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD1</name> + <description>Selects Reload Register number 1</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD2</name> + <description>Selects Reload Register number 2</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD3</name> + <description>Selects Reload Register number 3</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- IDR: Inc or dec Reload Register Selection --> + <field> + <name>IDR</name> + <description>Selects, if Reload Register number is incremented, decremented or not modified</description> + <bitRange>[27:26]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>KEEP</name> + <description>Reload Register number does not change automatically</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>INCREMENT</name> + <description>Reload Register number is incremented on each match</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>DECREMENT</name> + <description>Reload Register number is decremented on each match</description> + <value>2</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- START: Starts / Stops the Timer/Counter --> + <field> + <name>S</name> + <description>Starts and Stops the Timer / Counter</description> + <bitRange>[31:31]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>STOP</name> + <description>Timer / Counter is stopped</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>START</name> + <description>Timer / Counter is started</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + + <!-- SR: Status Register --> + <register> + <name>SR</name> + <description>Status Register</description> + <addressOffset>0x04</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xD701</resetMask> + + <fields> + <!-- RUN: Shows if Timer is running --> + <field> + <name>RUN</name> + <description>Shows if Timer is running or not</description> + <bitRange>[0:0]</bitRange> + <access>read-only</access> + <enumeratedValues> + <enumeratedValue> + <name>Stopped</name> + <description>Timer is not running</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Running</name> + <description>Timer is running</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- MATCH: Shows if a Match was hit --> + <field> + <name>MATCH</name> + <description>Shows if the MATCH was hit</description> + <bitRange>[8:8]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>No_Match</name> + <description>The MATCH condition was not hit</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Match_Hit</name> + <description>The MATCH condition was hit</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- UN: Shows if an underflow occured --> + <field> + <name>UN</name> + <description>Shows if an underflow occured. This flag is sticky</description> + <bitRange>[9:9]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>No_Underflow</name> + <description>No underflow occured since last clear</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Underflow</name> + <description>A minimum of one underflow occured since last clear</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- OV: Shows if an overflow occured --> + <field> + <name>OV</name> + <description>Shows if an overflow occured. This flag is sticky</description> + <bitRange>[10:10]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>No_Overflow</name> + <description>No overflow occured since last clear</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Overflow_occured</name> + <description>A minimum of one overflow occured since last clear</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- RST: Shows if Timer is in RESET state --> + <field> + <name>RST</name> + <description>Shows if Timer is in RESET state</description> + <bitRange>[12:12]</bitRange> + <access>read-only</access> + <enumeratedValues> + <enumeratedValue> + <name>Ready</name> + <description>Timer is not in RESET state and can operate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>In_Reset</name> + <description>Timer is in RESET state and can not operate</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- RELOAD: Shows the currently active Reload Register --> + <field> + <name>RELOAD</name> + <description>Shows the currently active RELOAD Register</description> + <bitRange>[15:14]</bitRange> + <access>read-only</access> + <enumeratedValues> + <enumeratedValue> + <name>RELOAD0</name> + <description>Reload Register number 0 is active</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD1</name> + <description>Reload Register number 1 is active</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD2</name> + <description>Reload Register number 2 is active</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>RELOAD3</name> + <description>Reload Register number 3 is active</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + + <!-- INT: Interrupt Register --> + <register> + <name>INT</name> + <description>Interrupt Register</description> + <addressOffset>0x10</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0x0771</resetMask> + + <fields> + <!-- EN: Interrupt Enable --> + <field> + <name>EN</name> + <description>Interrupt Enable</description> + <bitRange>[0:0]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Disabled</name> + <description>Timer does not generate Interrupts</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Enable</name> + <description>Timer triggers the TIMERn Interrupt</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + + <!-- MODE: Interrupt Mode --> + <field> + <name>MODE</name> + <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description> + <bitRange>[6:4]</bitRange> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>Match</name> + <description>Timer generates an Interrupt when the MATCH condition is hit</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>Underflow</name> + <description>Timer generates an Interrupt when it underflows</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>Overflow</name> + <description>Timer generates an Interrupt when it overflows</description> + <value>2</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + + <!-- COUNT: Counter Register --> + <register> + <name>COUNT</name> + <description>The Counter Register reflects the actual Value of the Timer/Counter</description> + <addressOffset>0x20</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + </register> + + <!-- MATCH: Match Register --> + <register> + <name>MATCH</name> + <description>The Match Register stores the compare Value for the MATCH condition</description> + <addressOffset>0x24</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + </register> + + <!-- PRESCALE: Prescale Read Register --> + <register> + <name>PRESCALE_RD</name> + <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description> + <addressOffset>0x28</addressOffset> + <size>32</size> + <access>read-only</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + </register> + + <!-- PRESCALE: Prescale Write Register --> + <register> + <name>PRESCALE_WR</name> + <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description> + <addressOffset>0x28</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + </register> + + + <!-- RELOAD: Array of Reload Register with 4 elements--> + <register> + <dim>4</dim> + <dimIncrement>4</dimIncrement> + <dimIndex>0,1,2,3</dimIndex> + <name>RELOAD[%s]</name> + <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description> + <addressOffset>0x50</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x00000000</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + </register> + </registers> + </peripheral> + + <!-- Timer 1 --> + <peripheral derivedFrom="TIMER0"> + <name>TIMER1</name> + <baseAddress>0x40010100</baseAddress> + <interrupt> + <name>TIMER1</name> + <value>4</value> + </interrupt> + </peripheral> + + <!-- Timer 2 --> + <peripheral derivedFrom="TIMER0"> + <name>TIMER2</name> + <baseAddress>0x40010200</baseAddress> + <interrupt> + <name>TIMER2</name> + <value>6</value> + </interrupt> + </peripheral> + </peripherals> +</device> +</pre></div> </div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html new file mode 100644 index 0000000..4f51d29 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html @@ -0,0 +1,104 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>CMSIS-SVD Web Interface User Guide</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('svd_web_pg.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">CMSIS-SVD Web Interface User Guide </div> </div> +</div> +<div class="contents"> +<div class="textblock"><p>The CMSIS Web Interface provides functionalities for downloading and managing the CMSIS-SVD files.</p> +<ul> +<li><a class="el" href="svd_web_public_pg.html">Public Download Area</a> - Users can download CMSIS-SVD files.</li> +<li><a class="el" href="svd_web_restricted_pg.html">Restricted Management Area</a> - Silicon Vendors can manage their devices and associated CMSIS-SVD files.</li> +</ul> +<p>In any case, the ARM web page requires login credentials to grant access to the content.</p> +<ul> +<li>Registration starts here: <a href="https://login.arm.com/register.php" target="_blank"><b>ARM Registration</b></a>. </li> +</ul> +</div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="index.html">System View Description</a> </li> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html new file mode 100644 index 0000000..da40503 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html @@ -0,0 +1,131 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Public Download Area</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('svd_web_public_pg.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Public Download Area </div> </div> +</div> +<div class="contents"> +<div class="textblock"><p>Public access to the Device Database is provided from <a href="http://cmsis.arm.com" target="_blank">cmsis.arm.com</a>. For the public download of the CMSIS-SVD files of published devices it is mandatory to:</p> +<ul> +<li>Be logged in on the ARM web site.</li> +<li>Have accepted a silicon vendor specific End Users License Agreement (EULA).</li> +</ul> +<h2><a class="anchor" id="login_downl_sec"></a> +Logging in</h2> +<ul> +<li>Use your credentials to <a href="https://login.arm.com/login.php" target="_blank"><b>Login</b></a>.</li> +</ul> +<h2><a class="anchor" id="open_downl_sec"></a> +Opening the CMSIS-SVD Download page</h2> +<div class="image"> +<img src="Access_SVD_Vendor.png" alt="Access_SVD_Vendor.png"/> +<div class="caption"> +Access Silicon Vendor Device Database</div></div> +<ul> +<li>Access the CMSIS webpage at <a href="http://cmsis.arm.com" target="_blank"><b>cmsis.arm.com</b></a>.</li> +<li>Select the "CMSIS-SVD" tab.</li> +<li>Click on a Silicon Vendor's name for getting redirected to the respective vendor device database.</li> +</ul> +<h2><a class="anchor" id="accept_EULA_sec"></a> +Accepting the Silicon Vendor's License terms</h2> +<p>On your first visit to a vendor database page you will be asked to review and accept the vendor-specific "End User License Agreement" (EULA). If you do not accept the EULA, you will see the list of devices and associated CMSIS-SVD files, but you will not be able to download any of the files. Note, in case the EULA has changed, you will be asked to review and accept the EULA again.</p> +<h2><a class="anchor" id="downl_downl_sec"></a> +Downloading CMSIS-SVD files</h2> +<div class="image"> +<img src="CMSIS_SVD_Vendor_DD.png" alt="CMSIS_SVD_Vendor_DD.png"/> +<div class="caption"> +Download Device Database Files</div></div> +<ul> +<li>Select one, multiple, or all devices from the table.</li> +<li>Click the "download" button.</li> +</ul> +<p>You will be asked to open or save the zip archive file containing the files. If you have selected multiple devices, the file <em>contents.txt</em> included in the archive will list the mapping between devices and CMSIS-SVD files. Multiple devices can share the same CMSIS-SVD file. </p> +</div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="index.html">System View Description</a> </li> + <li class="navelem"><a class="el" href="svd_web_pg.html">CMSIS-SVD Web Interface User Guide</a> </li> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html new file mode 100644 index 0000000..3de6cba --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html @@ -0,0 +1,157 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>Restricted Management Area</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('svd_web_restricted_pg.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">Restricted Management Area </div> </div> +</div> +<div class="contents"> +<div class="textblock"><p>Access to the CMSIS-SVD device database management system is restricted to:</p> +<ul> +<li>Silicon Vendors.</li> +<li>Companies who have signed an agreement with ARM about using the CMSIS-SVD device database.</li> +<li>ARM Cortex-M based microcontroller devices.</li> +</ul> +<h2><a class="anchor" id="sign_agreement_sec"></a> +Signing the agreement</h2> +<ul> +<li>The Silicon Vendor contacts the ARM sales representative or sends an email to <a href="mailto:cmsis@arm.com">cmsis@arm.com</a> requesting to contribute to the CMSIS-SVD Database.</li> +<li>An agreement needs to be signed between the Silicon Vendor and ARM defining the terms of use and specifying the representatives authorized for managing the files and devices.</li> +<li>The login e-mail addresses for www.arm.com get listed in the contract. The representatives need to ensure that their login already exists.</li> +<li>As part of exercising the contract the representatives will be given CMSIS-SVD Upload permissions in the system.</li> +</ul> +<h2><a class="anchor" id="login_mgmnt_dd_sec"></a> +Logging in</h2> +<ul> +<li>Use your credentials to <a href="https://login.arm.com/login.php" target="_blank"><b>Login</b></a>.</li> +</ul> +<h2><a class="anchor" id="open_mgmnt_ss_sec"></a> +Opening the CMSIS-SVD Device Database page</h2> +<div class="image"> +<img src="Access_SVD_DD_Manage.png" alt="Access_SVD_DD_Manage.png"/> +<div class="caption"> +Management Access to Device Database</div></div> +<ul> +<li>Access the CMSIS web page at <a href="http://cmsis.arm.com" target="_blank"><b>cmsis.arm.com</b></a>.</li> +<li>Click the button "Device Database" <dl class="note"><dt><b>Note:</b></dt><dd>If you do not see this button, you are either not logged in or you have not been granted CMSIS-SVD Upload permissions.</dd></dl> +</li> +</ul> +<h2><a class="anchor" id="manage_dd_entries_sec"></a> +Managing the Device Database</h2> +<p>The database lists microcontroller devices and their associated CMSIS-SVD files and, optionally, resource files. Multiple devices may share the same CMSIS-SVD and the optional resource file. For this reason, files and devices are managed separately. Files need to be uploaded and have to pass the check against the CMSIS-SVD Schema as well as the plausibility and consistency check by the SVDConv utility before they can be used to define a device. The SVDConv checking is scheduled. Therefore, it can take up to 15 minutes before the file status gets updated.</p> +<div class="image"> +<img src="Manage_SVD_DD.png" alt="Manage_SVD_DD.png"/> +<div class="caption"> +Manage Device Database Entries</div></div> +<ul> +<li>a) Manage Files<ul> +<li>Add <a href="file:">file:</a> Select the CMSIS-SVD file and start the upload process. The schema check will run immediately after the file upload is complete. If the check fails the file will not be stored and you are asked to upload a corrected file. The SVDConv check for this file is automatically scheduled and will take place within 15 minutes. The status of the file will be updated and reports errors and warnings in a text file that can be downloaded (click on error/warning respectively).</li> +<li>Delete <a href="file:">file:</a> Files can only be deleted if they are not associated with a device otherwise the system will list the devices the file is still associated with.</li> +<li>Replace <a href="file:">file:</a> Replace files allows you to update a file without the need to edit the device definition.</li> +</ul> +</li> +</ul> +<ul> +<li>b) Manage Devices <br/> + New devices can be added or existing devices can be edited. A device defines:<ul> +<li>Name of device</li> +<li>Filename CMSIS-SVD</li> +<li>Filename Resource zip archive</li> +<li>Reviewer List</li> +<li>Publishing Date <br/> + A checkbox is in front of each device to enable and disable a device. A disabled device will not show in the vendor-specific download area.</li> +</ul> +</li> +</ul> +<ul> +<li>c) Review Devices <br/> + Ask you reviewer for the login email address being used for the login on the ARM web. Add this email address into the field, one email address per line. You can add some text to the e-mail body however the email template already contains all relevant information like the device name as well as a link to the device database. </li> +</ul> +</div></div> +</div> + <div id="nav-path" class="navpath"> + <ul> + <li class="navelem"><a class="el" href="index.html">System View Description</a> </li> + <li class="navelem"><a class="el" href="svd_web_pg.html">CMSIS-SVD Web Interface User Guide</a> </li> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_a.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_a.png Binary files differnew file mode 100644 index 0000000..2d99ef2 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_a.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_h.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_h.png Binary files differnew file mode 100644 index 0000000..c11f48f --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_h.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_topnav.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_topnav.png Binary files differnew file mode 100644 index 0000000..b257b77 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_topnav.png diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tabs.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_common_tables.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000..8c35ef2 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,38 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef[6144]; +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..a965537 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1757 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ +#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/RTOS/cmsis_os.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/RTOS/cmsis_os.h new file mode 100644 index 0000000..2ccfd17 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/RTOS/cmsis_os.h @@ -0,0 +1,717 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * $Date: 5. March 2012 + * $Revision: V0.03 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behaviour + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * -------------------------------------------------------------------- */ + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +<b>Name conventions and header file modifications</b> + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +<b>Function calls from interrupt service routines</b> + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +<b>Define and reference object definitions</b> + +With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file +that is used troughtout a project as shown below: + +<i>Header File</i> +\code +#include <cmsis_os.h> // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +<i>Example</i> +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version +#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available + +#include <stdint.h> +#include <stddef.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Start the RTOS Kernel with executing the specified thread. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (osThreadDef_t *thread_def, void *argument); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread defintion. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay) +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signal); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signal); + +/// Get Signal Flags status of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS. +int32_t osSignalGet (osThreadId thread_id); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex defintion. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +#endif // Semaphore available + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of objects (elements) in the memory pool. +/// \param type data type of a single object (element). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can shall filled with mail or NULL in case error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/SVDConv.exe b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/SVDConv.exe Binary files differnew file mode 100644 index 0000000..6008adc --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/SVDConv.exe |
