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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html new file mode 100644 index 0000000..cadd4e0 --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html @@ -0,0 +1,507 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>TPI_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-CORE +  <span id="projectnumber">Version 3.01</span> + </div> + <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return 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initNavTree('struct_t_p_i___type.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">TPI_Type Struct Reference</div> </div> +</div> +<div class="contents"> +<!-- doxytag: class="TPI_Type" --> +<p>Structure type to access the Trace Port Interface Register (TPI). +</p> +<table class="memberdecls"> +<tr><td colspan="2"><h2><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">SSPSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) Supported Parallel Port Size Register. <a href="#a158e9d784f6ee6398f4bdcb2e4ca0912"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">CSPSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Current Parallel Port Size Register. <a href="#aa723ef3d38237aa2465779b3cc73a94a"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">RESERVED0</a> [2]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#af143c5e8fc9a3b2be2878e9c1f331aa9"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">ACPR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. <a href="#ad75832a669eb121f6fce3c28d36b7fab"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">RESERVED1</a> [55]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac3956fe93987b725d89d3be32738da12"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">SPPR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F0 (R/W) Selected Pin Protocol Register. <a href="#a3eb655f2e45d7af358775025c1a50c8e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">RESERVED2</a> [131]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac7bbb92e6231b9b38ac483f7d161a096"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">FFSR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/ ) Formatter and Flush Status Register. <a href="#ae67849b2c1016fe6ef9095827d16cddd"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">FFCR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x304 (R/W) Formatter and Flush Control Register. <a href="#a3eb42d69922e340037692424a69da880"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">FSCR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. <a href="#a377b78fe804f327e6f8b3d0f37e7bfef"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c">RESERVED3</a> [759]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a31700c8cdd26e4c094db72af33d9f24c"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TRIGGER</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEE8 (R/ ) TRIGGER. <a href="#aa4b603c71768dbda553da571eccba1fe"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">FIFO0</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEEC (R/ ) Integration ETM Data. <a href="#ae91ff529e87d8e234343ed31bcdc4f10"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">ITATBCTR2</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF0 (R/ ) ITATBCTR2. <a href="#a176d991adb4c022bd5b982a9f8fa6a1d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">RESERVED4</a> [1]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a684071216fafee4e80be6aaa932cec46"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">ITATBCTR0</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF8 (R/ ) ITATBCTR0. <a href="#a20ca7fad4d4009c242f20a7b4a44b7d0"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e">FIFO1</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEFC (R/ ) Integration ITM Data. <a href="#aebaa9b8dd27f8017dd4f92ecf32bac8e"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198">ITCTRL</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF00 (R/W) Integration Mode Control. <a href="#ab49c2cb6b5fe082746a444e07548c198"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">RESERVED5</a> [39]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a3f80dd93f6bab6524603a7aa58de9a30"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">CLAIMSET</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA0 (R/W) Claim tag set. <a href="#a2e4d5a07fabd771fa942a171230a0a84"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">CLAIMCLR</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA4 (R/W) Claim tag clear. <a href="#a44efa6045512c8d4da64b0623f7a43ad"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">RESERVED7</a> [8]</td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a476ca23fbc9480f1697fbec871130550"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">DEVID</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFC8 (R/ ) TPIU_DEVID. <a href="#a4b2e0d680cf7e26728ca8966363a938d"></a><br/></td></tr> +<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">DEVTYPE</a></td></tr> +<tr><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFCC (R/ ) TPIU_DEVTYPE. <a href="#a16d12c5b1e12f764fa3ec4a51c5f0f35"></a><br/></td></tr> +</table> +<hr/><h2>Field Documentation</h2> +<a class="anchor" id="ad75832a669eb121f6fce3c28d36b7fab"></a><!-- doxytag: member="TPI_Type::ACPR" ref="ad75832a669eb121f6fce3c28d36b7fab" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">TPI_Type::ACPR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a44efa6045512c8d4da64b0623f7a43ad"></a><!-- doxytag: member="TPI_Type::CLAIMCLR" ref="a44efa6045512c8d4da64b0623f7a43ad" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">TPI_Type::CLAIMCLR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2e4d5a07fabd771fa942a171230a0a84"></a><!-- doxytag: member="TPI_Type::CLAIMSET" ref="a2e4d5a07fabd771fa942a171230a0a84" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">TPI_Type::CLAIMSET</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="aa723ef3d38237aa2465779b3cc73a94a"></a><!-- doxytag: member="TPI_Type::CSPSR" ref="aa723ef3d38237aa2465779b3cc73a94a" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">TPI_Type::CSPSR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4b2e0d680cf7e26728ca8966363a938d"></a><!-- doxytag: member="TPI_Type::DEVID" ref="a4b2e0d680cf7e26728ca8966363a938d" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">TPI_Type::DEVID</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a16d12c5b1e12f764fa3ec4a51c5f0f35"></a><!-- doxytag: member="TPI_Type::DEVTYPE" ref="a16d12c5b1e12f764fa3ec4a51c5f0f35" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">TPI_Type::DEVTYPE</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3eb42d69922e340037692424a69da880"></a><!-- doxytag: member="TPI_Type::FFCR" ref="a3eb42d69922e340037692424a69da880" args="" --> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">TPI_Type::FFCR</a></td> + </tr> + </table> +</div> +<div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ae67849b2c1016fe6ef9095827d16cddd"></a><!-- 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