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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html new file mode 100644 index 0000000..ccc93af --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html @@ -0,0 +1,152 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<title>CPU Section (New)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> + + +</head> +<body> +<div id="top"><!-- do not remove this div! --> + +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td> + + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.10</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + + + + </tr> + </tbody> +</table> +</div> + +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li> + <li><a href="../../Core/html/index.html"><span>CORE</span></a></li> + <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li> + <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li> + <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li> + </ul> +</div> +<!-- Generated by Doxygen 1.7.5.1 --> +<script type="text/javascript" src="dynsections.js"></script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> + initNavTree('group__cpu_section__gr.html',''); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">CPU Section (New)</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div> +<div class="contents"> +<p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.</p> +<pre> +<span class="opt"><cpu></span> + <span class="mand"><name><em>cpuNameType</em><name> + <revision><em>revisionType</em><revision> + <endian><em>endianType</em><endian> + <mpuPresent><em>xs:boolean</em><mpuPresent> + <fpuPresent><em>xs:boolean</em><fpuPresent> + <nvicPrioBits><em>scaledNonNegativeInteger</em><nvicPrioBits> + <vendorSystickConfig><em>xs:boolean</em><vendorSystickConfig></span> +<span class="opt"></cpu></span> +</pre><table class="cmtable" summary="CPU Section Elements"> +<tr> +<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>The predefined tokens are:<ul> +<li><span class="XML-Token">CM0</span>: ARM Cortex-M0</li> +<li><span class="XML-Token">CM0PLUS</span>: ARM Cortex-M0+</li> +<li><span class="XML-Token">CM3</span>: ARM Cortex-M3</li> +<li><span class="XML-Token">CM4</span>: ARM Cortex-M4</li> +<li><span class="XML-Token">SC000</span>: ARM Secure Core SC000</li> +<li><span class="XML-Token">SC300</span>: ARM Secure Core SC300</li> +<li><span class="XML-Token">other</span>: other processor architectures </li> +</ul> +</td><td>cpuNameType </td><td>1..1 </td></tr> +<tr> +<td>revisionType </td><td>Defines the HW revision of the processor. The defined version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 9]). </td><td>revisionType </td><td>1..1 </td></tr> +<tr> +<td>endian </td><td>Defines the endianess of the processor being one of:<ul> +<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li> +<li><span class="XML-Token">other</span>: the endianess is neither little nor big endian. </li> +</ul> +</td><td>endianType </td><td>1..1 </td></tr> +<tr> +<td>mpuPresent </td><td>Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>fpuPresent </td><td>Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>nvicPrioBits </td><td>Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr> +<td>vendorSystickConfig </td><td>Indicates whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the ARM defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +</table> +<h2><a class="anchor" id="cpuSection_ex"></a> +Example:</h2> +<div class="fragment"><pre class="fragment">... +<cpu> + <name>CM4</name> + <revision>r0p0</revision> + <endian>little</endian> + <mpuPresent><span class="keyword">true</span></mpuPresent> + <fpuPresent><span class="keyword">true</span></fpuPresent> + <nvicPrioBits>4</nvicPrioBits> + <vendorSystickConfig><span class="keyword">false</span></vendorSystickConfig> +</cpu> +... +</pre></div><p>This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. </p> +</div> +</div> + <div id="nav-path" class="navpath"> + <ul> + + <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li> + --> + </li> + </ul> + </div> + + +</body> +</html> |