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path: root/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
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Diffstat (limited to 'stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c')
-rw-r--r--stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c154
1 files changed, 77 insertions, 77 deletions
diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
index c0cc7d1..7f863f5 100644
--- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
+++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
@@ -5,10 +5,10 @@
* @version V1.0.4
* @date 29-April-2016
* @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
- *
+ *
******************************************************************************
* @attention
*
@@ -36,8 +36,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -78,22 +78,22 @@
* @{
*/
-/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief Extended Peripheral Control functions
+/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the RCC Clocks
+ This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
- [..]
+ [..]
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) are set to their reset values.
-
+
@endverbatim
* @{
*/
@@ -104,12 +104,12 @@
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(RTC clock).
*
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) are set to their reset values.
*
- * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
+ * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
* one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
* manually disable it.
*
@@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*------------------------------- RTC/LCD Configuration ------------------------*/
+
+ /*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
{
/* check for RTC Parameters used to output RTCCLK */
@@ -133,22 +133,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
-
+
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -165,32 +165,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
{
/* Get timeout */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
- /*------------------------------ ADC clock Configuration ------------------*/
+ /*------------------------------ ADC clock Configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
-
+
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
}
#if defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ I2S2 Configuration ------------------------*/
+ /*------------------------------ I2S2 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
{
/* Check the parameters */
@@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
}
- /*------------------------------ I2S3 Configuration ------------------------*/
+ /*------------------------------ I2S3 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
{
/* Check the parameters */
assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
-
+
/* Configure the I2S3 clock source */
__HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
}
- /*------------------------------ PLL I2S Configuration ----------------------*/
+ /*------------------------------ PLL I2S Configuration ----------------------*/
/* Check that PLLI2S need to be enabled */
if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
{
@@ -241,13 +241,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the main PLLI2S multiplication factors. */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
-
+
/* Enable the main PLLI2S. */
__HAL_RCC_PLLI2S_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
@@ -271,12 +271,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ USB clock Configuration ------------------*/
+ /*------------------------------ USB clock Configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
-
+
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
}
@@ -288,14 +288,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/**
* @brief Get the PeriphClkInit according to the internal
* RCC configuration registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t srcclk = 0;
-
+
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
@@ -410,17 +410,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
+
switch (PeriphClk)
{
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
- case RCC_PERIPHCLK_USB:
+ case RCC_PERIPHCLK_USB:
{
/* Get RCC configuration ------------------------------------------------------*/
temp_reg = RCC->CFGR;
-
+
/* Check if PLL is enabled */
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
{
@@ -448,7 +448,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
}
-
+
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
/* In this case need to divide pllclk by 2 */
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
@@ -474,12 +474,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
{
- /* Prescaler of 2 selected for USB */
+ /* Prescaler of 2 selected for USB */
frequency = pllclk;
}
else
{
- /* Prescaler of 3 selected for USB */
+ /* Prescaler of 3 selected for USB */
frequency = (2 * pllclk) / 3;
}
#else
@@ -491,7 +491,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
else
{
- /* Prescaler of 1.5 selected for USB */
+ /* Prescaler of 1.5 selected for USB */
frequency = (pllclk * 2) / 3;
}
#endif
@@ -501,7 +501,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|| defined(STM32F107xC)
- case RCC_PERIPHCLK_I2S2:
+ case RCC_PERIPHCLK_I2S2:
{
#if defined(STM32F103xE) || defined(STM32F103xG)
/* SYSCLK used as source clock for I2S2 */
@@ -552,7 +552,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break;
}
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
- case RCC_PERIPHCLK_RTC:
+ case RCC_PERIPHCLK_RTC:
{
/* Get RCC BDCR configuration ------------------------------------------------------*/
temp_reg = RCC->BDCR;
@@ -578,12 +578,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
- case RCC_PERIPHCLK_ADC:
+ case RCC_PERIPHCLK_ADC:
{
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
break;
}
- default:
+ default:
{
break;
}
@@ -599,10 +599,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
* @brief PLLI2S Management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Extended PLLI2S Management functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the PLLI2S
activation or deactivation
@@ -641,8 +641,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
+
+ /* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
@@ -653,17 +653,17 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
-
+
/* Configure the main PLLI2S multiplication factors. */
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
-
+
/* Enable the main PLLI2S. */
__HAL_RCC_PLLI2S_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
@@ -699,8 +699,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
+
+ /* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
@@ -714,7 +714,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
/* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
return HAL_ERROR;
}
-
+
return HAL_OK;
}
@@ -725,10 +725,10 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
* @brief PLL2 Management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Extended PLL2 Management functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the PLL2
activation or deactivation
@@ -747,7 +747,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
{
uint32_t tickstart = 0;
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
@@ -771,10 +771,10 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
/* Disable the main PLL2. */
__HAL_RCC_PLL2_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till PLL2 is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
{
@@ -783,19 +783,19 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
return HAL_TIMEOUT;
}
}
-
+
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
/* Configure the main PLL2 multiplication factors. */
__HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
-
+
/* Enable the main PLL2. */
__HAL_RCC_PLL2_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till PLL2 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
{
@@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
{
uint32_t tickstart = 0;
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
@@ -833,8 +833,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
+
+ /* Wait till PLL2 is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-06 19:14:29 +0000