diff options
Diffstat (limited to 'stm32cubemx/Drivers/STM32F1xx_HAL_Driver')
33 files changed, 2243 insertions, 2243 deletions
diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 9325273..8b2bd1c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -60,7 +60,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -92,10 +92,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -111,21 +111,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -150,7 +150,7 @@ #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -214,7 +214,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -231,7 +231,7 @@ #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE ((uint32_t)0x00000000U) #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -243,28 +243,28 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -272,7 +272,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -347,11 +347,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -364,7 +364,7 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ @@ -387,7 +387,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -420,17 +420,17 @@ #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -456,7 +456,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -529,7 +529,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -559,7 +559,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -583,11 +583,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -596,14 +596,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -612,7 +612,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -624,18 +624,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -648,11 +648,11 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD @@ -662,17 +662,17 @@ #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -680,15 +680,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -709,7 +709,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -727,7 +727,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -743,13 +743,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -848,7 +848,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -888,7 +888,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -902,18 +902,18 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) +#define ETH_MMCCR ((uint32_t)0x00000100U) +#define ETH_MMCRIR ((uint32_t)0x00000104U) +#define ETH_MMCTIR ((uint32_t)0x00000108U) +#define ETH_MMCRIMR ((uint32_t)0x0000010CU) +#define ETH_MMCTIMR ((uint32_t)0x00000110U) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) +#define ETH_MMCTGFCR ((uint32_t)0x00000168U) +#define ETH_MMCRFCECR ((uint32_t)0x00000194U) +#define ETH_MMCRFAECR ((uint32_t)0x00000198U) #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) - + #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ @@ -948,7 +948,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -963,39 +963,39 @@ /** * @} - */ - + */ + #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4xx || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1008,11 +1008,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1022,12 +1022,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1035,7 +1035,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1129,17 +1129,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1150,7 +1150,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1162,28 +1162,28 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1198,8 +1198,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1208,7 +1208,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1227,7 +1227,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1324,7 +1324,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1397,7 +1397,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1584,7 +1584,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1603,11 +1603,11 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE @@ -1626,11 +1626,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1641,7 +1641,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1650,7 +1650,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1679,8 +1679,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1745,7 +1745,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1753,17 +1753,17 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI @@ -1780,8 +1780,8 @@ #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET @@ -2219,13 +2219,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE @@ -2278,111 +2278,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2390,29 +2390,29 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2638,7 +2638,7 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY #if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE +#define RCC_IT_LSECSS RCC_IT_CSSLSE #define RCC_IT_CSS RCC_IT_CSSHSE #endif @@ -2769,16 +2769,16 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2815,7 +2815,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2842,24 +2842,24 @@ #if defined(STM32F4) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2868,8 +2868,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2909,7 +2909,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2941,7 +2941,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -2953,8 +2953,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3059,7 +3059,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3068,7 +3068,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3108,7 +3108,7 @@ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h index c2f16d6..3b949f7 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains all the functions prototypes for the HAL + * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention @@ -34,7 +34,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_H @@ -53,7 +53,7 @@ /** @addtogroup HAL * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -65,33 +65,33 @@ */ /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode - * @brief Freeze/Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @{ */ - + /* Peripherals on APB1 */ /** - * @brief TIM2 Peripherals Debug mode + * @brief TIM2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) /** - * @brief TIM3 Peripherals Debug mode + * @brief TIM3 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #if defined (DBGMCU_CR_DBG_TIM4_STOP) /** - * @brief TIM4 Peripherals Debug mode + * @brief TIM4 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) @@ -99,7 +99,7 @@ #if defined (DBGMCU_CR_DBG_TIM5_STOP) /** - * @brief TIM5 Peripherals Debug mode + * @brief TIM5 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) @@ -107,7 +107,7 @@ #if defined (DBGMCU_CR_DBG_TIM6_STOP) /** - * @brief TIM6 Peripherals Debug mode + * @brief TIM6 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) @@ -115,7 +115,7 @@ #if defined (DBGMCU_CR_DBG_TIM7_STOP) /** - * @brief TIM7 Peripherals Debug mode + * @brief TIM7 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) @@ -123,7 +123,7 @@ #if defined (DBGMCU_CR_DBG_TIM12_STOP) /** - * @brief TIM12 Peripherals Debug mode + * @brief TIM12 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) @@ -131,7 +131,7 @@ #if defined (DBGMCU_CR_DBG_TIM13_STOP) /** - * @brief TIM13 Peripherals Debug mode + * @brief TIM13 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) @@ -139,33 +139,33 @@ #if defined (DBGMCU_CR_DBG_TIM14_STOP) /** - * @brief TIM14 Peripherals Debug mode + * @brief TIM14 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #endif /** - * @brief WWDG Peripherals Debug mode + * @brief WWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) /** - * @brief IWDG Peripherals Debug mode + * @brief IWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) /** - * @brief I2C1 Peripherals Debug mode + * @brief I2C1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) /** - * @brief I2C2 Peripherals Debug mode + * @brief I2C2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) @@ -173,7 +173,7 @@ #if defined (DBGMCU_CR_DBG_CAN1_STOP) /** - * @brief CAN1 Peripherals Debug mode + * @brief CAN1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) @@ -181,16 +181,16 @@ #if defined (DBGMCU_CR_DBG_CAN2_STOP) /** - * @brief CAN2 Peripherals Debug mode + * @brief CAN2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) -#endif - +#endif + /* Peripherals on APB2 */ #if defined (DBGMCU_CR_DBG_TIM1_STOP) /** - * @brief TIM1 Peripherals Debug mode + * @brief TIM1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) @@ -198,7 +198,7 @@ #if defined (DBGMCU_CR_DBG_TIM8_STOP) /** - * @brief TIM8 Peripherals Debug mode + * @brief TIM8 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) @@ -206,7 +206,7 @@ #if defined (DBGMCU_CR_DBG_TIM9_STOP) /** - * @brief TIM9 Peripherals Debug mode + * @brief TIM9 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) @@ -214,7 +214,7 @@ #if defined (DBGMCU_CR_DBG_TIM10_STOP) /** - * @brief TIM10 Peripherals Debug mode + * @brief TIM10 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) @@ -222,7 +222,7 @@ #if defined (DBGMCU_CR_DBG_TIM11_STOP) /** - * @brief TIM11 Peripherals Debug mode + * @brief TIM11 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) @@ -231,7 +231,7 @@ #if defined (DBGMCU_CR_DBG_TIM15_STOP) /** - * @brief TIM15 Peripherals Debug mode + * @brief TIM15 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) @@ -239,7 +239,7 @@ #if defined (DBGMCU_CR_DBG_TIM16_STOP) /** - * @brief TIM16 Peripherals Debug mode + * @brief TIM16 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) @@ -247,7 +247,7 @@ #if defined (DBGMCU_CR_DBG_TIM17_STOP) /** - * @brief TIM17 Peripherals Debug mode + * @brief TIM17 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) @@ -313,12 +313,12 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h index 30788b0..d2ee169 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_CORTEX_H @@ -52,7 +52,7 @@ /** @addtogroup CORTEX * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types Cortex Exported Types * @{ @@ -60,31 +60,31 @@ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure + * @brief MPU Region initialization structure * @{ */ typedef struct { - uint8_t Enable; /*!< Specifies the status of the region. + uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. + uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. + uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. + uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** @@ -102,7 +102,7 @@ typedef struct */ -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ @@ -134,7 +134,7 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) @@ -202,44 +202,44 @@ typedef struct */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** +/** * @} */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} @@ -248,11 +248,11 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) @@ -264,14 +264,14 @@ typedef struct /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ - */ + */ -/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group +/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ @@ -281,7 +281,7 @@ typedef struct ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - + #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) @@ -292,7 +292,7 @@ typedef struct /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source * @{ - */ + */ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) /** @@ -377,7 +377,7 @@ typedef struct /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); @@ -391,7 +391,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ #if (__MPU_PRESENT == 1) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); @@ -412,10 +412,10 @@ void HAL_SYSTICK_Callback(void); /** * @} */ - -/* Private functions ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ /** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions + * @brief CORTEX private functions * @{ */ @@ -428,15 +428,15 @@ __STATIC_INLINE void HAL_MPU_Disable(void) { /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - + /* Disable the MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI @@ -448,7 +448,7 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - + /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; } @@ -460,17 +460,17 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_CORTEX_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h index b0f1693..8600be2 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -4,8 +4,8 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. ****************************************************************************** * @attention * @@ -51,10 +51,10 @@ /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL Status structures definition - */ -typedef enum +/** + * @brief HAL Status structures definition + */ +typedef enum { HAL_OK = 0x00, HAL_ERROR = 0x01, @@ -62,13 +62,13 @@ typedef enum HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; -/** - * @brief HAL Lock structures definition +/** + * @brief HAL Lock structures definition */ -typedef enum +typedef enum { HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_LOCKED = 0x01 } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ @@ -88,11 +88,11 @@ typedef enum /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: + * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function + * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling @@ -139,62 +139,62 @@ typedef enum #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) + #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN + #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ -/** +/** * @brief __RAM_FUNC definition - */ + */ #if defined ( __CC_ARM ) /* ARM Compiler ------------ - RAM functions are defined using the toolchain options. + RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' + Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. + dialog. */ -#define __RAM_FUNC HAL_StatusTypeDef +#define __RAM_FUNC HAL_StatusTypeDef #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". + RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc HAL_StatusTypeDef #elif defined ( __GNUC__ ) /* GNU Compiler ------------ - RAM functions are defined using a specific toolchain attribute + RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) #endif -/** +/** * @brief __NOINLINE definition - */ + */ #if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +/* ARM & GNUCompiler + ---------------- */ -#define __NOINLINE __attribute__ ( (noinline) ) +#define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h index 5d344b2..d26fd60 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_H @@ -52,56 +52,56 @@ /** @addtogroup DMA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ - -/** + +/** * @brief DMA Configuration Structure definition */ typedef struct { - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ - + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ - + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ + data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; -/** +/** * @brief DMA Configuration enumeration values definition - */ -typedef enum + */ +typedef enum { DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ - + } DMA_ControlTypeDef; /** - * @brief HAL DMA State structures definition + * @brief HAL DMA State structures definition */ typedef enum { @@ -113,7 +113,7 @@ typedef enum HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ }HAL_DMA_StateTypeDef; -/** +/** * @brief HAL DMA Error Code structure definition */ typedef enum @@ -122,29 +122,29 @@ typedef enum HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; -/** +/** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - + + void *Parent; /*!< Parent object state */ + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - + __IO uint32_t ErrorCode; /*!< DMA Error code */ -} DMA_HandleTypeDef; +} DMA_HandleTypeDef; /** * @} */ @@ -168,7 +168,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ - */ + */ #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ @@ -179,16 +179,16 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ - */ + */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ /** * @} - */ + */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ - */ + */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ /** @@ -197,16 +197,16 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ - */ + */ #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} - */ + */ /** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ + * @{ */ #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ @@ -217,7 +217,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA mode * @{ - */ + */ #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** @@ -233,7 +233,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} - */ + */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions @@ -248,7 +248,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ - */ + */ #define DMA_FLAG_GL1 ((uint32_t)0x00000001) #define DMA_FLAG_TC1 ((uint32_t)0x00000002) #define DMA_FLAG_HT1 ((uint32_t)0x00000004) @@ -284,7 +284,7 @@ typedef struct __DMA_HandleTypeDef /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros @@ -317,7 +317,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -329,7 +329,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -353,7 +353,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. * @param __HANDLE__: DMA handle - * + * * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) @@ -363,14 +363,14 @@ typedef struct __DMA_HandleTypeDef */ /* Include DMA HAL Extension module */ -#include "stm32f1xx_hal_dma_ex.h" +#include "stm32f1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions DMA Exported Functions * @{ */ -/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); * @} */ -/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* IO operation functions *****************************************************/ @@ -409,16 +409,16 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /* Private Constants -------------------------------------------------------------*/ /** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants + * @brief DMA private defines and constants * @{ */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros + * @brief DMA private macros * @{ */ @@ -426,7 +426,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) @@ -443,20 +443,20 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) + ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions + * @brief DMA private functions * @{ */ /** @@ -465,7 +465,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h index 05d2d3a..ca3af14 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h @@ -52,9 +52,9 @@ /** @defgroup DMAEx DMAEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros @@ -90,7 +90,7 @@ * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -132,7 +132,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ @@ -147,7 +147,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ @@ -181,7 +181,7 @@ * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -213,7 +213,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ @@ -227,7 +227,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) @@ -237,7 +237,7 @@ */ #endif - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h index 1135f81..5f46d66 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -45,7 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" - + /** @addtogroup STM32F1xx_HAL_Driver * @{ */ @@ -53,7 +53,7 @@ /** @addtogroup FLASH * @{ */ - + /** @addtogroup FLASH_Private_Constants * @{ */ @@ -68,7 +68,7 @@ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) #if defined(FLASH_ACR_LATENCY) #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ @@ -80,20 +80,20 @@ #endif /* FLASH_ACR_LATENCY */ /** * @} - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ - */ + */ /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { - FLASH_PROC_NONE = 0, + FLASH_PROC_NONE = 0, FLASH_PROC_PAGEERASE = 1, FLASH_PROC_MASSERASE = 2, FLASH_PROC_PROGRAMHALFWORD = 3, @@ -101,13 +101,13 @@ typedef enum FLASH_PROC_PROGRAMDOUBLEWORD = 5 } FLASH_ProcedureTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ @@ -116,7 +116,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< FLASH locking object */ - __IO uint32_t ErrorCode; /*!< FLASH error code + __IO uint32_t ErrorCode; /*!< FLASH error code This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; @@ -127,7 +127,7 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ - */ + */ /** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ @@ -144,7 +144,7 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ - */ + */ #define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/ @@ -178,15 +178,15 @@ typedef struct #endif /* FLASH_ACR_LATENCY */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features + * @brief macros to control FLASH features * @{ */ - + /** @defgroup FLASH_Half_Cycle FLASH Half Cycle * @brief macros to handle FLASH half cycle * @{ @@ -216,22 +216,22 @@ typedef struct /** @defgroup FLASH_EM_Latency FLASH Latency * @brief macros to handle FLASH Latency * @{ - */ - + */ + /** * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval None - */ + */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * The value of this parameter depend on device used within the same series - */ + */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** @@ -242,11 +242,11 @@ typedef struct /** @defgroup FLASH_Prefetch FLASH Prefetch * @brief macros to handle FLASH Prefetch buffer * @{ - */ + */ /** * @brief Enable the FLASH prefetch buffer. * @retval None - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) /** @@ -258,19 +258,19 @@ typedef struct /** * @} */ - + /** * @} - */ + */ /* Include FLASH HAL Extended module */ -#include "stm32f1xx_hal_flash_ex.h" +#include "stm32f1xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ - + /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ @@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* FLASH IRQ handler function */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h index 933a95e..41375db 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h @@ -52,7 +52,7 @@ /** @addtogroup FLASHEx * @{ - */ + */ /** @addtogroup FLASHEx_Private_Constants * @{ @@ -64,7 +64,7 @@ /** * @} - */ + */ /** @addtogroup FLASHEx_Private_Macros * @{ @@ -74,11 +74,11 @@ #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) @@ -175,12 +175,12 @@ /** * @} - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types * @{ - */ + */ /** * @brief FLASH Erase structure definition @@ -189,17 +189,17 @@ typedef struct { uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ - + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ - + This parameter must be a value of @ref FLASHEx_Banks */ + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END + This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END (x = 1 or 2 depending on devices)*/ - + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ - + } FLASH_EraseInitTypeDef; /** @@ -217,26 +217,26 @@ typedef struct This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. - This parameter must be a value of @ref FLASHEx_Banks */ - + This parameter must be a value of @ref FLASHEx_Banks */ + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ #if defined(FLASH_BANK2_END) - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ #else - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY */ #endif /* FLASH_BANK2_END */ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of @ref FLASHEx_OB_Data_Address */ - + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ } FLASH_OBProgramInitTypeDef; @@ -248,15 +248,15 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ - */ + */ /** @defgroup FLASHEx_Constants FLASH Constants * @{ - */ + */ /** @defgroup FLASHEx_Page_Size Page Size * @{ - */ + */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define FLASH_PAGE_SIZE ((uint32_t)0x400) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ @@ -265,7 +265,7 @@ typedef struct #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) #define FLASH_PAGE_SIZE ((uint32_t)0x800) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - /* STM32F101xG || STM32F103xG */ + /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ /** @@ -274,7 +274,7 @@ typedef struct /** @defgroup FLASHEx_Type_Erase Type Erase * @{ - */ + */ #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/ @@ -303,7 +303,7 @@ typedef struct /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants * @{ - */ + */ /** @defgroup FLASHEx_OB_Type Option Bytes Type * @{ @@ -319,7 +319,7 @@ typedef struct /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State * @{ - */ + */ #define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/ #define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/ @@ -344,7 +344,7 @@ typedef struct #define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - + /* STM32 Medium-density devices */ #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) #define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */ @@ -413,11 +413,11 @@ typedef struct #define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */ #define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - /* STM32F101xG || STM32F103xG */ + /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ #define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - + /* Low Density */ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) #define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF) @@ -430,9 +430,9 @@ typedef struct #define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000) #define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ - + /* High Density */ -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00) #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000) @@ -440,13 +440,13 @@ typedef struct #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ -#if defined(STM32F101xG) || defined(STM32F103xG) +#if defined(STM32F101xG) || defined(STM32F103xG) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00) #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000) #define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000) #endif /* STM32F101xG || STM32F103xG */ - + /* Connectivity line devices */ #if defined(STM32F105xC) || defined(STM32F107xC) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) @@ -467,10 +467,10 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog * @{ - */ + */ #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ /** @@ -479,16 +479,16 @@ typedef struct /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP * @{ - */ + */ #define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ /** * @} - */ + */ /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY * @{ - */ + */ #define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ /** @@ -521,31 +521,31 @@ typedef struct /** @addtogroup FLASHEx_Constants * @{ - */ + */ /** @defgroup FLASH_Flag_definition Flag definition * @brief Flag definition * @{ */ #if defined(FLASH_BANK2_END) - #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ + #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ - #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ + #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ - - #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */ + + #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */ -#else +#else - #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ @@ -555,7 +555,7 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Interrupt_definition Interrupt definition * @brief FLASH Interrupt definition * @{ @@ -578,12 +578,12 @@ typedef struct #endif /** * @} - */ + */ /** * @} */ - + /** * @} @@ -597,19 +597,19 @@ typedef struct /** @defgroup FLASH_Interrupt Interrupt * @brief macros to handle FLASH interrupts * @{ - */ + */ #if defined(FLASH_BANK2_END) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ /* Enable Bank1 IT */ \ SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \ @@ -619,14 +619,14 @@ typedef struct /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ /* Disable Bank1 IT */ \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \ @@ -635,7 +635,7 @@ typedef struct } while(0) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 @@ -692,30 +692,30 @@ typedef struct #else /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_BSY FLASH Busy flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match @@ -728,9 +728,9 @@ typedef struct * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h index 22cd019..e585410 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_H @@ -52,16 +52,16 @@ /** @addtogroup GPIO * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ - */ + */ -/** - * @brief GPIO Init structure definition - */ +/** + * @brief GPIO Init structure definition + */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. @@ -69,19 +69,19 @@ typedef struct uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ - + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull_define */ - + uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ }GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration + +/** + * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum -{ +{ GPIO_PIN_RESET = 0, GPIO_PIN_SET }GPIO_PinState; @@ -95,11 +95,11 @@ typedef enum /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ - */ + */ /** @defgroup GPIO_pins_define GPIO pins define * @{ - */ + */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ @@ -121,19 +121,19 @@ typedef enum #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ /** * @} - */ + */ + - /** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode + * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection + * - y : External IT or Event trigger detection * - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ - */ + */ #define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ @@ -142,11 +142,11 @@ typedef enum #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ - + #define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - + #define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ @@ -154,12 +154,12 @@ typedef enum /** * @} */ - - + + /** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ - */ + */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ @@ -172,7 +172,7 @@ typedef enum /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ - */ + */ #define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ #define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ @@ -180,7 +180,7 @@ typedef enum /** * @} */ - + /** * @} */ @@ -197,7 +197,7 @@ typedef enum #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ ((PULL) == GPIO_PULLDOWN)) - + #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) @@ -230,8 +230,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. @@ -246,8 +246,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. @@ -273,7 +273,7 @@ typedef enum -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /* Initialization and de-initialization functions *******************************/ /** @addtogroup GPIO_Exported_Functions * @{ @@ -304,15 +304,15 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h index 9d9c3b3..71d8735 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_EX_H @@ -52,7 +52,7 @@ /** @defgroup GPIOEx GPIOEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ @@ -60,17 +60,17 @@ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ - */ - + */ + /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration * @brief This section propose definition to use the Cortex EVENTOUT signal. * @{ */ - -/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin + +/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin * @{ */ - + #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ @@ -106,12 +106,12 @@ ((__PIN__) == AFIO_EVENTOUT_PIN_15)) /** * @} - */ - + */ + /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port * @{ */ - + #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ @@ -126,7 +126,7 @@ /** * @} */ - + /** * @} */ @@ -135,7 +135,7 @@ * @brief This section propose definition to remap the alternate function to some other port/pins. * @{ */ - + /** * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) @@ -327,9 +327,9 @@ #endif /** - * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used - * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and - * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. * @retval None @@ -337,9 +337,9 @@ #define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) /** - * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used - * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and - * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note DISABLE: No remapping of PD0 and PD1 * @retval None @@ -817,12 +817,12 @@ /** * @} - */ - + */ + /** * @} */ - + /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros * @{ */ @@ -864,20 +864,20 @@ void HAL_GPIOEx_DisableEventout(void); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h index 9489bd3..8dcc87f 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PCD_H @@ -57,9 +57,9 @@ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ @@ -90,12 +90,12 @@ typedef enum /** * @brief PCD endpoint buffer number */ -typedef enum +typedef enum { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 -}PCD_EP_BUF_NUM; +}PCD_EP_BUF_NUM; #endif /* USB */ #if defined (USB_OTG_FS) @@ -110,14 +110,14 @@ typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; #endif /* USB */ -/** +/** * @brief PCD Handle Structure definition */ typedef struct { PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ + __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ @@ -147,7 +147,7 @@ typedef struct /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ @@ -359,11 +359,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 #define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 /** * @} */ - + /** @defgroup PCD_ENDP PCD ENDP * @{ */ @@ -638,7 +638,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ PCD_TX_DTOG((USBx), (bEpNum)); \ } - + /** * @brief Sets address in an endpoint register. * @param USBx: USB peripheral instance register address. @@ -655,7 +655,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) - + #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ @@ -777,9 +777,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @brief Gets buffer 0/1 address of a double buffer endpoint. * @param USBx: USB peripheral instance register address. * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value * @retval None */ #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ @@ -825,7 +825,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} */ - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h index 5e13c73..7e20d30 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PCD_EX_H @@ -75,7 +75,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* USB_OTG_FS */ #if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); @@ -96,7 +96,7 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); */ /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h index b5f78ca..0c52f59 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h @@ -58,7 +58,7 @@ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ - */ + */ /** * @brief PWR PVD configuration structure definition @@ -82,7 +82,7 @@ typedef struct /** @addtogroup PWR_Private_Constants * @{ - */ + */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ @@ -90,12 +90,12 @@ typedef struct * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ - */ + */ /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ @@ -107,8 +107,8 @@ typedef struct #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 - +#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 + /** * @} */ @@ -222,7 +222,7 @@ typedef struct #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** - * @brief Disable interrupt on PVD Exti Line 16. + * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) @@ -241,7 +241,7 @@ typedef struct /** - * @brief PVD EXTI line configuration: set falling edge trigger. + * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) @@ -316,7 +316,7 @@ typedef struct #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) + ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) @@ -338,8 +338,8 @@ typedef struct /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -352,7 +352,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h index b893074..0ef33fe 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h @@ -60,8 +60,8 @@ /** @defgroup RCC_Timeout RCC Timeout * @{ - */ - + */ + /* Disable Backup domain write protection state change timeout */ #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ /* LSE state change timeout */ @@ -75,7 +75,7 @@ /** * @} */ - + /** @defgroup RCC_Register_Offset Register offsets * @{ */ @@ -143,7 +143,7 @@ /** * @} */ - + /* CR register byte 2 (Bits[23:16]) base address */ #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) @@ -214,7 +214,7 @@ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ @@ -230,8 +230,8 @@ * @{ */ -/** - * @brief RCC PLL configuration structure definition +/** + * @brief RCC PLL configuration structure definition */ typedef struct { @@ -239,14 +239,14 @@ typedef struct This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ } RCC_PLLInitTypeDef; - + /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { @@ -402,7 +402,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ @@ -458,8 +458,8 @@ typedef struct #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} - */ - + */ + /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register @@ -503,8 +503,8 @@ typedef struct /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ @@ -572,9 +572,9 @@ typedef struct /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ + * is disabled and the application software has to enable this clock before + * using it. + * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -675,9 +675,9 @@ typedef struct /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. - * @{ + * @{ */ #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -765,7 +765,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -799,9 +799,9 @@ typedef struct /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. - * @{ + * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) @@ -811,7 +811,7 @@ typedef struct #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) @@ -827,9 +827,9 @@ typedef struct /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. - * @{ + * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) @@ -841,7 +841,7 @@ typedef struct #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) @@ -858,18 +858,18 @@ typedef struct */ /** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) @@ -880,7 +880,7 @@ typedef struct * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. - */ + */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) @@ -889,20 +889,20 @@ typedef struct */ /** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ + * @{ */ /** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) /** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. + * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) @@ -911,7 +911,7 @@ typedef struct */ /** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ + * @{ */ /** @@ -964,16 +964,16 @@ typedef struct */ /** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ + * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. @@ -1012,11 +1012,11 @@ typedef struct */ /** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ + * @{ */ /** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on + * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. @@ -1030,7 +1030,7 @@ typedef struct /** @brief Macro to configure the main PLL clock source and multiplication factors. * @note This function must be used only when the main PLL is disabled. - * + * * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry @@ -1056,7 +1056,7 @@ typedef struct @endif * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 - * + * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) @@ -1074,7 +1074,7 @@ typedef struct */ /** @defgroup RCC_Get_Clock_source Get Clock source - * @{ + * @{ */ /** @@ -1102,8 +1102,8 @@ typedef struct */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ + * @{ + */ #if defined(RCC_CFGR_MCO_3) /** @brief Macro to configure the MCO clock. @@ -1146,15 +1146,15 @@ typedef struct */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ + * @{ */ /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * @@ -1167,12 +1167,12 @@ typedef struct * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. + * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - + /** @brief Macro to get the RTC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock @@ -1384,7 +1384,7 @@ void HAL_RCC_CSSCallback(void); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h index 4d38a3a..9871f4a 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_EX_H @@ -52,7 +52,7 @@ /** @addtogroup RCCEx * @{ - */ + */ /** @addtogroup RCCEx_Private_Constants * @{ @@ -73,7 +73,7 @@ #endif /* STM32F105xC || STM32F107xC */ -#define CR_REG_INDEX ((uint8_t)1) +#define CR_REG_INDEX ((uint8_t)1) /** * @} @@ -213,15 +213,15 @@ * @} */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLL2 configuration structure definition +/** + * @brief RCC PLL2 configuration structure definition */ typedef struct { @@ -229,7 +229,7 @@ typedef struct This parameter can be a value of @ref RCCEx_PLL2_Config */ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock - This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ + This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. @@ -240,8 +240,8 @@ typedef struct #endif /* STM32F105xC || STM32F107xC */ -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { @@ -255,37 +255,37 @@ typedef struct uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ - + uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) This parameter can be a value of @ref RCCEx_Prediv1_Factor */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ - + uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - + uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ #if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ + RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ #endif /* STM32F105xC || STM32F107xC */ } RCC_OscInitTypeDef; #if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLLI2S configuration structure definition +/** + * @brief RCC PLLI2S configuration structure definition */ typedef struct { uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock - This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ + This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. @@ -295,8 +295,8 @@ typedef struct } RCC_PLLI2SInitTypeDef; #endif /* STM32F105xC || STM32F107xC */ -/** - * @brief RCC extended clocks structure definition +/** + * @brief RCC extended clocks structure definition */ typedef struct { @@ -306,7 +306,7 @@ typedef struct uint32_t RTCClockSelection; /*!< specifies the RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ - uint32_t AdcClockSelection; /*!< ADC clock source + uint32_t AdcClockSelection; /*!< ADC clock source This parameter can be a value of @ref RCCEx_ADC_Prescaler */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ @@ -316,9 +316,9 @@ typedef struct uint32_t I2s3ClockSelection; /*!< I2S3 clock source This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ - + #if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ #endif /* STM32F105xC || STM32F107xC */ @@ -327,7 +327,7 @@ typedef struct #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - uint32_t UsbClockSelection; /*!< USB clock source + uint32_t UsbClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Prescaler */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ @@ -607,7 +607,7 @@ typedef struct #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) /** * @} - */ + */ /** @defgroup RCCEx_Flag RCCEx Flag * Elements values convention: 0XXYYYYYb @@ -621,7 +621,7 @@ typedef struct #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY))) /** * @} - */ + */ #endif /* STM32F105xC || STM32F107xC*/ /** @@ -636,8 +636,8 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ @@ -739,7 +739,7 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) - + #endif /* STM32F107xC*/ /** @@ -789,9 +789,9 @@ typedef struct /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ + * is disabled and the application software has to enable this clock before + * using it. + * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ @@ -1174,9 +1174,9 @@ typedef struct /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. - * @{ + * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ @@ -1401,7 +1401,7 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release * @brief Force or release AHB peripheral reset. * @{ - */ + */ #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) @@ -1421,7 +1421,7 @@ typedef struct /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. - * @{ + * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ @@ -1523,7 +1523,7 @@ typedef struct /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. - * @{ + * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ @@ -1593,8 +1593,8 @@ typedef struct */ /** @defgroup RCCEx_HSE_Configuration HSE Configuration - * @{ - */ + * @{ + */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) @@ -1642,11 +1642,11 @@ typedef struct #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable the main PLLI2S. - * @note After enabling the main PLLI2S, the application software should wait on + * @note After enabling the main PLLI2S, the application software should wait on * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can * be used as system clock source. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. @@ -1660,7 +1660,7 @@ typedef struct /** @brief macros to configure the main PLLI2S multiplication factor. * @note This function must be used only when the main PLLI2S is disabled. - * + * * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 @@ -1672,7 +1672,7 @@ typedef struct * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 - * + * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) @@ -1686,7 +1686,7 @@ typedef struct /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration * @brief Macros to configure clock source of different peripherals. * @{ - */ + */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) @@ -1755,8 +1755,8 @@ typedef struct #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_HSE_Configuration - * @{ - */ + * @{ + */ /** * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. @@ -1768,7 +1768,7 @@ typedef struct */ #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) - + /** * @brief Macro to get prediv2 factor for PLL2 & PLL3. */ @@ -1779,11 +1779,11 @@ typedef struct */ /** @addtogroup RCCEx_PLLI2S_Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable the main PLL2. - * @note After enabling the main PLL2, the application software should wait on + * @note After enabling the main PLL2, the application software should wait on * PLL2RDY flag to be set indicating that PLL2 clock is stable and can * be used as system clock source. * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. @@ -1798,7 +1798,7 @@ typedef struct /** @brief macros to configure the main PLL2 multiplication factor. * @note This function must be used only when the main PLL2 is disabled. - * + * * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 @@ -1810,7 +1810,7 @@ typedef struct * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 - * + * */ #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) @@ -1822,7 +1822,7 @@ typedef struct /** @defgroup RCCEx_I2S_Configuration I2S Configuration * @brief Macros to configure clock source of I2S peripherals. * @{ - */ + */ /** @brief Macro to configure the I2S2 clock. * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. @@ -1911,11 +1911,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); /** * @} */ - + /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h index 70e27ef..7e1c530 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -890,7 +890,7 @@ typedef struct #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ ((MODE) == TIM_OCMODE_PWM2)) - + #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ ((MODE) == TIM_OCMODE_ACTIVE) || \ ((MODE) == TIM_OCMODE_INACTIVE) || \ @@ -918,10 +918,10 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_ALL)) - + #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - + ((CHANNEL) == TIM_CHANNEL_2)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)) @@ -944,7 +944,7 @@ typedef struct #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) + ((MODE) == TIM_ENCODERMODE_TI12)) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) @@ -970,9 +970,9 @@ typedef struct #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ @@ -1301,7 +1301,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag @@ -1322,7 +1322,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag @@ -1532,11 +1532,11 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__: Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h index e26cedc..b6410ac 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_TIM_EX_H @@ -52,31 +52,31 @@ /** @addtogroup TIMEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIMEx Exported Types * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; @@ -84,9 +84,9 @@ typedef struct defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ defined (STM32F105xC) || defined (STM32F107xC) -/** - * @brief TIM Break and Dead time configuration Structure definition - */ +/** + * @brief TIM Break and Dead time configuration Structure definition + */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode @@ -94,34 +94,34 @@ typedef struct uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State + uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity + uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F105xC) || defined(STM32F107xC) */ -/** - * @brief TIM Master configuration Structure definition - */ +/** + * @brief TIM Master configuration Structure definition + */ typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode */ }TIM_MasterConfigTypeDef; /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ #if defined (STM32F100xB) || defined (STM32F100xE) || \ @@ -130,7 +130,7 @@ typedef struct { /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ - + /** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter * @{ */ @@ -281,7 +281,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /** * @} - */ + */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ @@ -291,17 +291,17 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** * @} -*/ +*/ /* End of private functions --------------------------------------------------*/ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h index d9d59f5..3579c3d 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h @@ -63,10 +63,10 @@ /** @defgroup USB_LL_Exported_Types USB Low Layer Exported Types * @{ */ -/** - * @brief USB Mode definition +/** + * @brief USB Mode definition */ -typedef enum +typedef enum { USB_DEVICE_MODE = 0, USB_HOST_MODE = 1, @@ -86,7 +86,7 @@ typedef enum { URB_STALL }USB_OTG_URBStateTypeDef; -/** +/** * @brief Host channel States definition */ typedef enum { @@ -96,36 +96,36 @@ typedef enum { HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR }USB_OTG_HCStateTypeDef; -/** - * @brief USB OTG Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. + This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. This parameter can be any value of @ref USB_EP0_MPS_ */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ }USB_OTG_CfgTypeDef; @@ -133,34 +133,34 @@ typedef struct { uint8_t num; /*!< Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_EP_Type_ */ - + uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - + uint32_t xfer_len; /*!< Current transfer length */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ }USB_OTG_EPTypeDef; @@ -168,81 +168,81 @@ typedef struct { uint8_t dev_addr ; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - + uint8_t ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t ep_num; /*!< Endpoint number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t speed; /*!< USB Host speed. This parameter can be any value of @ref USB_Core_Speed_ */ - + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ - + uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_EP_Type_ */ - + uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t data_pid; /*!< Initial data PID. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - + uint32_t xfer_len; /*!< Current transfer length. */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - + uint8_t toggle_in; /*!< IN transfer current toggle flag. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - + uint32_t ErrCnt; /*!< Host channel error count.*/ - + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ }USB_OTG_HCTypeDef; #endif /* USB_OTG_FS */ #if defined (USB) -/** - * @brief USB Initialization Structure definition +/** + * @brief USB Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. + This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. This parameter can be any value of @ref USB_EP0_MPS */ - + uint32_t phy_itface; /*!< Select the used PHY interface. This parameter can be any value of @ref USB_Core_PHY */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; @@ -250,39 +250,39 @@ typedef struct { uint8_t num; /*!< Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_EP_Type */ - + uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr0; /*!< PMA Address0 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr1; /*!< PMA Address1 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral + + uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral This parameter is added to ensure compatibility across USB peripherals */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t xfer_len; /*!< Current transfer length */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_EPTypeDef; @@ -447,7 +447,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) #endif /* USB_OTG_FS */ -#if defined (USB) +#if defined (USB) /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -457,7 +457,7 @@ typedef struct #define DEP0CTL_MPS_8 3 /** * @} - */ + */ /** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ @@ -469,7 +469,7 @@ typedef struct #define EP_TYPE_MSK 3 /** * @} - */ + */ #define BTABLE_ADDRESS (0x000) #endif /* USB */ @@ -537,7 +537,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -595,7 +595,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c index 0e0af69..19a4699 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -13,9 +13,9 @@ ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. + used by the PPP peripheral drivers and the user to start using the HAL. [..] - The HAL contains two APIs' categories: + The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @@ -109,7 +109,7 @@ static __IO uint32_t uwTick; * @{ */ -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim @@ -117,36 +117,36 @@ static __IO uint32_t uwTick; ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file. - + @endverbatim * @{ */ /** - * @brief This function configures the Flash prefetch, + * @brief This function configures the Flash prefetch, * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before + * @note This function is called at the beginning of program after reset and before * the clock configuration * @note The time base configuration is based on MSI clock when exiting from Reset. * Once done, time base tick start incrementing. @@ -200,10 +200,10 @@ HAL_StatusTypeDef HAL_DeInit(void) __HAL_RCC_AHB_FORCE_RESET(); __HAL_RCC_AHB_RELEASE_RESET(); #endif - + /* De-Init the low level hardware */ HAL_MspDeInit(); - + /* Return function status */ return HAL_OK; } @@ -231,15 +231,15 @@ __weak void HAL_MspDeInit(void) } /** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. @@ -262,7 +262,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -280,7 +280,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) (+) Enable/Disable Debug module during Sleep mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode - + @endverbatim * @{ */ @@ -290,7 +290,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -301,7 +301,7 @@ __weak void HAL_IncTick(void) /** * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ @@ -311,7 +311,7 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function provides accurate delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick @@ -334,7 +334,7 @@ __weak void HAL_Delay(__IO uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment + * is called, the the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -350,7 +350,7 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment + * is called, the the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -377,7 +377,7 @@ uint32_t HAL_GetHalVersion(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device revision identifier @@ -393,7 +393,7 @@ uint32_t HAL_GetREVID(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device identifier @@ -418,7 +418,7 @@ void HAL_DBGMCU_EnableDBGSleepMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -434,18 +434,18 @@ void HAL_DBGMCU_DisableDBGSleepMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode + * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. - * Workaround: To debug the Stop mode, disable the system tick timer + * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode + * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer @@ -464,7 +464,7 @@ void HAL_DBGMCU_EnableDBGStopMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -480,7 +480,7 @@ void HAL_DBGMCU_DisableDBGStopMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -496,7 +496,7 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c index 1c9d886..836503c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c @@ -10,19 +10,19 @@ * functionalities of the CORTEX: * + Initialization and de-initialization functions * + Peripheral Control functions - * - * @verbatim + * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] *** How to configure Interrupts using Cortex HAL driver *** =========================================================== - [..] + [..] This section provide functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M3 exceptions are managed by CMSIS functions. - + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. @@ -36,35 +36,35 @@ -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority + | | | 0 bits for subpriority ========================================================================================================================== - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. - + -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest pre-emption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) - - [..] + + [..] *** How to configure Systick using Cortex HAL driver *** ======================================================== [..] Setup SysTick Timer for 1 msec interrupts. - + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. @@ -73,21 +73,21 @@ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: - + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF - + @endverbatim ****************************************************************************** * @attention @@ -146,15 +146,15 @@ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provide the Cortex HAL driver functions allowing to configure Interrupts - Systick functionalities + Systick functionalities @endverbatim * @{ @@ -164,7 +164,7 @@ /** * @brief Sets the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority * 4 bits for subpriority @@ -176,15 +176,15 @@ * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } @@ -196,29 +196,29 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority + * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. + * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup = 0x00; - + /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - + prioritygroup = NVIC_GetPriorityGrouping(); - + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. + * function should be called before. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) @@ -237,7 +237,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) @@ -276,17 +276,17 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions + * @brief Cortex control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - + (NVIC, SYSTICK, MPU) functionalities. + + @endverbatim * @{ */ @@ -318,7 +318,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - + MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | @@ -381,26 +381,26 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPre * @brief Sets Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ +{ /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ +{ /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -409,11 +409,11 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) * @brief Clears the pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ +{ /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -422,12 +422,12 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ +{ /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c index 4a48d5f..a249c81 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -5,56 +5,56 @@ * @version V1.0.4 * @date 29-April-2016 * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is + (except for internal SRAM / FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals and DMA requests. - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, using HAL_DMA_Init() function. - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. - + (#) Use HAL_DMA_Abort() function to abort the current transfer - + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. - *** Interrupt mode IO operation *** - =================================== + *** Interrupt mode IO operation *** + =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). *** DMA HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DMA HAL driver. @@ -64,10 +64,10 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** @@ -98,7 +98,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -142,41 +142,41 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, + and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. + reference manual. @endverbatim * @{ */ - + /** * @brief Initializes the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ +{ uint32_t tmp = 0; - + /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); @@ -186,24 +186,24 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - + if(hdma->State == HAL_DMA_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; } - + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; - + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); - + /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | @@ -211,21 +211,21 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - + hdma->Instance->CCR = tmp; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the DMA peripheral + * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) @@ -235,7 +235,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); @@ -247,16 +247,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - + /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; - + /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; - + /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; - + /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0; @@ -264,7 +264,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -281,20 +281,20 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete - (+) Handle DMA interrupt request + (+) Handle DMA interrupt request @endverbatim * @{ @@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Starts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -319,23 +319,23 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - return HAL_OK; + return HAL_OK; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -351,50 +351,50 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the transfer complete interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); /* Enable the transfer Error interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - + return HAL_OK; -} +} /** * @brief Aborts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * - * @note After disabling a DMA Channel, a check for wait until the DMA Channel is - * effectively disabled is added. If a Channel is disabled + * + * @note After disabling a DMA Channel, a check for wait until the DMA Channel is + * effectively disabled is added. If a Channel is disabled * while a data transfer is ongoing, the current data will be transferred * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. + * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { uint32_t tickstart = 0x00; - + /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Get tick */ tickstart = HAL_GetTick(); - + /* Check if the DMA Channel is effectively disabled */ while((hdma->Instance->CCR & DMA_CCR_EN) != 0) { @@ -415,10 +415,10 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_OK; } @@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { uint32_t temp; uint32_t tickstart = 0x00; - + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { @@ -453,19 +453,19 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) - { + { /* Clear the transfer error flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_ERROR; } /* Check for the Timeout */ @@ -475,13 +475,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } @@ -492,21 +492,21 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - /* The selected Channelx EN bit is cleared (DMA is disabled and + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else - { + { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and + + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers of half buffer are complete) */ hdma->State = HAL_DMA_STATE_READY_HALF; } - + /* Process unlocked */ __HAL_UNLOCK(hdma); @@ -516,7 +516,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /** * @brief Handles DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) @@ -528,19 +528,19 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Disable the transfer error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - + /* Clear the transfer error flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma); - + __HAL_UNLOCK(hdma); + if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ @@ -553,7 +553,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { + { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { @@ -573,7 +573,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } } - + /* Transfer Complete Interrupt management ***********************************/ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) { @@ -586,18 +586,18 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + if(hdma->XferCpltCallback != NULL) - { + { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } @@ -610,9 +610,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### State and Errors functions ##### =============================================================================== @@ -628,7 +628,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Returns the DMA state. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) @@ -662,7 +662,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -672,13 +672,13 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t { /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - + /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - + /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } @@ -687,7 +687,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; - + /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c index b5d6c1a..b59e08c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c @@ -5,22 +5,22 @@ * @version V1.0.4 * @date 29-April-2016 * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions - * + Memory Control functions + * + Memory Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. + prefetch. [..] The FLASH main features are: (+) Flash memory read operations @@ -32,16 +32,16 @@ ##### How to use this driver ##### ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH + [..] + This driver provides functions and macros to configure and program the FLASH memory of all STM32F1xx devices. - + (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword - + (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes @@ -53,22 +53,22 @@ (++) Program the data Option Bytes (++) Get the Write protection. (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group + + (#) Interrupts and flags management functions : this group includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status - (++) Get error flag status + (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: - + (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the half cycle access (+) Enable/Disable the FLASH interrupts (+) Monitor the FLASH flags status - + @endverbatim ****************************************************************************** * @attention @@ -97,7 +97,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -127,7 +127,7 @@ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ - + /** * @} */ @@ -156,11 +156,11 @@ static void FLASH_SetErrorCode(void); /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions * -@verbatim +@verbatim @endverbatim * @{ */ @@ -170,17 +170,17 @@ static void FLASH_SetErrorCode(void); * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * - * @note If an erase and a program operations are requested simultaneously, + * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. - * - * @note FLASH should be previously erased before new programmation (only exception to this + * + * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) @@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef status = HAL_ERROR; uint8_t index = 0; uint8_t nbiterations = 0; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ - + if(status == HAL_OK) { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) @@ -239,7 +239,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) @@ -248,7 +248,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } @@ -272,20 +272,20 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * - * @note If an erase and a program operations are requested simultaneously, + * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -299,7 +299,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u { return HAL_ERROR; } - + if(Address <= FLASH_BANK1_END) { /* Enable End of FLASH Operation and Error source interrupts */ @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ - + pFlash.Address = Address; pFlash.Data = Data; @@ -350,7 +350,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0; - + /* Check FLASH operation error flags */ #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ @@ -363,10 +363,10 @@ void HAL_FLASH_IRQHandler(void) addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFF; - + /*Save the Error code*/ FLASH_SetErrorCode(); - + /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); @@ -386,7 +386,7 @@ void HAL_FLASH_IRQHandler(void) /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); #endif /* FLASH_BANK2_END */ - + /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { @@ -445,17 +445,17 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still 16-bit data to program */ if(pFlash.DataRemaining != 0) { /* Increment address to 16-bit */ pFlash.Address += 2; addresstmp = pFlash.Address; - + /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16); - + /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -474,11 +474,11 @@ void HAL_FLASH_IRQHandler(void) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2); } - else + else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); } - + /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -486,14 +486,14 @@ void HAL_FLASH_IRQHandler(void) } } } - + #if defined(FLASH_BANK2_END) /* Check FLASH End of Operation flag */ if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); - + /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { @@ -501,13 +501,13 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still pages to erase*/ if(pFlash.DataRemaining != 0) { /* Indicate user which page address has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Address); - + /* Increment page address to next page */ pFlash.Address += FLASH_PAGE_SIZE; addresstmp = pFlash.Address; @@ -520,7 +520,7 @@ void HAL_FLASH_IRQHandler(void) else { /*No more pages to Erase*/ - + /*Reset Address and stop Erase pages procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -539,7 +539,7 @@ void HAL_FLASH_IRQHandler(void) /* MassErase ended. Return the selected bank*/ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0); - + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } @@ -547,17 +547,17 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still 16-bit data to program */ if(pFlash.DataRemaining != 0) { /* Increment address to 16-bit */ pFlash.Address += 2; addresstmp = pFlash.Address; - + /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16); - + /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); @@ -576,11 +576,11 @@ void HAL_FLASH_IRQHandler(void) { HAL_FLASH_EndOfOperationCallback(pFlash.Address-2); } - else + else { HAL_FLASH_EndOfOperationCallback(pFlash.Address-6); } - + /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -588,15 +588,15 @@ void HAL_FLASH_IRQHandler(void) } } } -#endif +#endif if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { #if defined(FLASH_BANK2_END) /* Operation is completed, disable the PG, PER and MER Bits for both bank */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); - + CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); + /* Disable End of FLASH Operation and Error source interrupts for both banks */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #else @@ -617,7 +617,7 @@ void HAL_FLASH_IRQHandler(void) * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which has been erased + * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none @@ -628,7 +628,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ + */ } /** @@ -645,22 +645,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim @@ -695,9 +695,9 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { return HAL_ERROR; } - + #endif /* FLASH_BANK2_END */ - return HAL_OK; + return HAL_OK; } /** @@ -708,13 +708,13 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - + #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ - return HAL_OK; + return HAL_OK; } @@ -733,23 +733,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) else { return HAL_ERROR; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); - - return HAL_OK; + + return HAL_OK; } - + /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. @@ -759,21 +759,21 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Initiates a system reset request to launch the option byte loading */ HAL_NVIC_SystemReset(); - - return HAL_OK; + + return HAL_OK; } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permit to get in run-time the status of the FLASH peripheral. @@ -787,9 +787,9 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; -} +} /** * @} */ @@ -812,7 +812,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - + #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { @@ -842,11 +842,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { if (Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) @@ -855,16 +855,16 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } } } - + /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ @@ -883,15 +883,15 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) -{ +{ /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) - { + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) + { if (Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) @@ -900,7 +900,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) } } } - + /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { @@ -917,7 +917,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) /* If there is an error flag set */ return HAL_OK; - + } #endif /* FLASH_BANK2_END */ @@ -926,7 +926,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) * @retval None */ static void FLASH_SetErrorCode(void) -{ +{ #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else @@ -956,7 +956,7 @@ static void FLASH_SetErrorCode(void) #else __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); #endif /* FLASH_BANK2_END */ -} +} /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c index 91e4d5a..0416efe 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c @@ -5,27 +5,27 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions - * + Extended Peripheral Control functions - * + * + Extended Peripheral Control functions + * @verbatim ============================================================================== ##### Flash peripheral extended features ##### ============================================================================== - + ##### How to use this driver ##### ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory + [..] This driver provides functions to configure and program the FLASH memory of all STM32F1xxx devices. It includes - + (++) Set/Reset the write protection (++) Program the user Option Bytes (++) Get the Read protection Level - + @endverbatim ****************************************************************************** * @attention @@ -54,7 +54,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -80,7 +80,7 @@ extern FLASH_ProcessTypeDef pFlash; /** * @} */ - + /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ @@ -104,7 +104,7 @@ extern FLASH_ProcessTypeDef pFlash; */ /** * @} - */ + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -132,37 +132,37 @@ static uint8_t FLASH_OB_GetUser(void); /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ - + /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * -@verbatim +@verbatim ============================================================================== - ##### FLASH Erasing Programming functions ##### + ##### FLASH Erasing Programming functions ##### ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ - + /** * @brief Perform a mass erase or erase the specified FLASH memory pages * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. @@ -196,14 +196,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_BOTH); - + /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { status = HAL_OK; } - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); @@ -217,15 +217,15 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_2); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } - else + else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ @@ -234,10 +234,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); } @@ -249,30 +249,30 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - + #if defined(FLASH_BANK2_END) /* Page Erase requested on address located on bank2 */ if(pEraseInit->PageAddress > FLASH_BANK1_END) - { + { /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFF; - + /* Erase by page by page to be done*/ for(address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); - + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ @@ -291,20 +291,20 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFF; - + /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ @@ -326,7 +326,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. @@ -345,7 +345,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); @@ -355,7 +355,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) #if defined(FLASH_BANK2_END) /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); - + #endif if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { @@ -389,12 +389,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions * @brief Option Bytes Programming functions * -@verbatim +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH option bytes operations. @endverbatim @@ -566,7 +566,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { uint32_t value = 0; - + if (DATAAdress == OB_DATA_ADDRESS_DATA0) { /* Get value programmed in OB USER Data0 */ @@ -577,7 +577,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) /* Get value programmed in OB USER Data1 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; } - + return value; } @@ -594,7 +594,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) */ /** - * @brief Full erase of FLASH memory Bank + * @brief Full erase of FLASH memory Bank * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg @ref FLASH_BANK_1 Bank1 to be erased @@ -645,14 +645,14 @@ static void FLASH_MassErase(uint32_t Banks) /** * @brief Enable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * * @param WriteProtectPage specifies the page(s) to be write protected. - * The value of this parameter depend on device used within the same series - * @retval HAL status + * The value of this parameter depend on device used within the same series + * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { @@ -667,25 +667,25 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ - + /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); - + /* Get current write protected pages and the new pages to be protected ******/ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); - + #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ - + #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); #endif /* OB_WRP_PAGES32TO63MASK */ - + #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); #endif /* OB_WRP_PAGES64TO95MASK */ @@ -694,26 +694,26 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); #endif /* OB_WRP_PAGES96TO127MASK */ - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) + if (status == HAL_OK) { /* Enable write protection */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); @@ -722,7 +722,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if(WRP0_Data != 0xFF) { OB->WRP0 &= WRP0_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -732,7 +732,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP1_Data != 0xFF)) { OB->WRP1 &= WRP1_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -742,7 +742,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP2_Data != 0xFF)) { OB->WRP2 &= WRP2_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -752,7 +752,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP3_Data != 0xFF)) { OB->WRP3 &= WRP3_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -762,20 +762,20 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } - + return status; } /** * @brief Disable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * * @param WriteProtectPage specifies the page(s) to be write unprotected. - * The value of this parameter depend on device used within the same series - * @retval HAL status + * The value of this parameter depend on device used within the same series + * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { @@ -790,7 +790,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ - + /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); @@ -802,13 +802,13 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ - + #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); #endif /* OB_WRP_PAGES32TO63MASK */ - + #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); #endif /* OB_WRP_PAGES64TO95MASK */ @@ -817,27 +817,27 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); #endif /* OB_WRP_PAGES96TO127MASK */ - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) + if (status == HAL_OK) { SET_BIT(FLASH->CR, FLASH_CR_OPTPG); @@ -845,7 +845,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if(WRP0_Data != 0xFF) { OB->WRP0 |= WRP0_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -855,7 +855,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP1_Data != 0xFF)) { OB->WRP1 |= WRP1_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -865,7 +865,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP2_Data != 0xFF)) { OB->WRP2 |= WRP2_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -875,7 +875,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP3_Data != 0xFF)) { OB->WRP3 |= WRP3_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -899,18 +899,18 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - + /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); @@ -925,26 +925,26 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - + WRITE_REG(OB->RDP, ReadProtectLevel); - + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } - + return status; } /** - * @brief Program the FLASH User Option Byte. + * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), + * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . + * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) @@ -961,15 +961,15 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + #if defined(FLASH_BANK2_END) OB->USER = (UserConfig | 0xF0); #else @@ -982,44 +982,44 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } - - return status; + + return status; } /** * @brief Programs a half word at a specified Option Byte Data address. * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param Address specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data specifies the data to be programmed. * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t*)Address = Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } @@ -1048,7 +1048,7 @@ static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; uint32_t tmp_reg = 0; - + /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); @@ -1056,7 +1056,7 @@ static uint32_t FLASH_OB_GetRDP(void) { readstatus = OB_RDP_LEVEL_1; } - else + else { readstatus = OB_RDP_LEVEL_0; } @@ -1066,9 +1066,9 @@ static uint32_t FLASH_OB_GetRDP(void) /** * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . + * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . */ static uint8_t FLASH_OB_GetUser(void) { @@ -1095,8 +1095,8 @@ static uint8_t FLASH_OB_GetUser(void) /** * @brief Erase the specified FLASH memory page * @param PageAddress FLASH page to erase - * The value of this parameter depend on device used within the same series - * + * The value of this parameter depend on device used within the same series + * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) @@ -1106,7 +1106,7 @@ void FLASH_PageErase(uint32_t PageAddress) #if defined(FLASH_BANK2_END) if(PageAddress > FLASH_BANK1_END) - { + { /* Proceed to erase the page */ SET_BIT(FLASH->CR2, FLASH_CR2_PER); WRITE_REG(FLASH->AR2, PageAddress); diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index 9e048ad..4e7c78a 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -5,89 +5,89 @@ * @version V1.0.4 * @date 29-April-2016 * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral features ##### - ============================================================================== - [..] + ============================================================================== + [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: - (+) Input mode + (+) Input mode (+) Analog mode (+) Output mode (+) Alternate function mode (+) External interrupt/event lines - [..] - During and just after reset, the alternate functions and external interrupt + [..] + During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. [..] In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] + + [..] The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests - + ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). - + ============================================================================== + [..] + (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. - (++) In case of Output or alternate function mode selection: the speed is + (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure - (++) Analog mode is required when a pin is to be used as ADC channel + (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). - + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use + + (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not + + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PD0 and PD1, respectively, when the HSE oscillator is off. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. - + @endverbatim ****************************************************************************** * @attention @@ -116,8 +116,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -138,14 +138,14 @@ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ - + #define GPIO_MODE ((uint32_t)0x00000003) #define EXTI_MODE ((uint32_t)0x10000000) #define GPIO_MODE_IT ((uint32_t)0x00010000) #define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) #define GPIO_NUMBER ((uint32_t)16) /* Definitions for bit manipulation of CRL and CRH register */ @@ -157,7 +157,7 @@ #define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */ #define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */ #define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */ - + /** * @} */ @@ -174,14 +174,14 @@ /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and deinitialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs to be ready for use. - + @endverbatim * @{ */ @@ -202,7 +202,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) uint32_t config = 0x00; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); @@ -213,7 +213,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; - + /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; @@ -231,28 +231,28 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; break; - + /* If we are configuring the pin in OUTPUT open-drain mode */ case GPIO_MODE_OUTPUT_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; break; - + /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ case GPIO_MODE_AF_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; break; - + /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ case GPIO_MODE_AF_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; break; - + /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ case GPIO_MODE_INPUT: case GPIO_MODE_IT_RISING: @@ -264,46 +264,46 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the GPIO pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); if(GPIO_Init->Pull == GPIO_NOPULL) - { + { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; } else if(GPIO_Init->Pull == GPIO_PULLUP) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - + /* Set the corresponding ODR bit */ GPIOx->BSRR = ioposition; } else /* GPIO_PULLDOWN */ { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - + /* Reset the corresponding ODR bit */ GPIOx->BRR = ioposition; } - break; - + break; + /* If we are configuring the pin in INPUT analog mode */ case GPIO_MODE_ANALOG: config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; - + /* Parameters are checked with assert_param */ default: break; } - + /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); - + /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset)); - + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); @@ -311,46 +311,46 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); AFIO->EXTICR[position >> 2] = temp; - + /* Configure the interrupt mask */ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { - SET_BIT(EXTI->IMR, iocurrent); - } + SET_BIT(EXTI->IMR, iocurrent); + } else { - CLEAR_BIT(EXTI->IMR, iocurrent); - } - + CLEAR_BIT(EXTI->IMR, iocurrent); + } + /* Configure the event mask */ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { - SET_BIT(EXTI->EMR, iocurrent); - } + SET_BIT(EXTI->EMR, iocurrent); + } else { - CLEAR_BIT(EXTI->EMR, iocurrent); + CLEAR_BIT(EXTI->EMR, iocurrent); } - + /* Enable or disable the rising trigger */ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { - SET_BIT(EXTI->RTSR, iocurrent); - } + SET_BIT(EXTI->RTSR, iocurrent); + } else { - CLEAR_BIT(EXTI->RTSR, iocurrent); + CLEAR_BIT(EXTI->RTSR, iocurrent); } - + /* Enable or disable the falling trigger */ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { - SET_BIT(EXTI->FTSR, iocurrent); - } + SET_BIT(EXTI->FTSR, iocurrent); + } else { - CLEAR_BIT(EXTI->FTSR, iocurrent); + CLEAR_BIT(EXTI->FTSR, iocurrent); } } } @@ -365,13 +365,13 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ +{ uint32_t position = 0x00; uint32_t iocurrent = 0x00; uint32_t tmp = 0x00; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0; - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); @@ -389,33 +389,33 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); - + /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset); - + /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); - + /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - + tmp = AFIO->EXTICR[position >> 2]; tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) { tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp); - + /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - + /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); } } - + position++; } } @@ -424,10 +424,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -464,11 +464,11 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * + * * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). @@ -496,7 +496,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pin - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ @@ -555,8 +555,8 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } @@ -573,7 +573,7 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) UNUSED(GPIO_Pin); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c index 31493e6..da0b4a5 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c @@ -5,24 +5,24 @@ * @version V1.0.4 * @date 29-April-2016 * @brief GPIO Extension HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * + Extended features functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral extension features ##### - ============================================================================== + ============================================================================== [..] GPIO module on STM32F1 family, manage also the AFIO register: (+) Possibility to use the EVENTOUT Cortex feature - + ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to use EVENTOUT Cortex feature (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() - + @endverbatim ****************************************************************************** * @attention @@ -51,8 +51,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -73,21 +73,21 @@ */ /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions + * @brief Extended features functions * -@verbatim +@verbatim ============================================================================== ##### Extended features functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() - + @endverbatim * @{ */ - + /** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. @@ -95,13 +95,13 @@ * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * @retval None - */ + */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) { /* Verify the parameters */ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); - + /* Apply the new configuration */ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource)); } @@ -127,11 +127,11 @@ void HAL_GPIOEx_DisableEventout(void) /** * @} */ - + /** * @} */ - + #endif /* HAL_GPIO_MODULE_ENABLED */ /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c index 91461a3..42d38ae 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c @@ -5,11 +5,11 @@ * @version V1.0.4 * @date 29-April-2016 * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions * @verbatim @@ -31,7 +31,7 @@ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available on STM32F102xx and STM32F103xx devices (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available - on STM32F105xx and STM32F107xx devices + on STM32F105xx and STM32F107xx devices (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -101,7 +101,7 @@ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ - */ + */ #define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) /** @@ -128,15 +128,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); * @{ */ -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ @@ -150,36 +150,36 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { uint32_t index = 0; - + /* Check the PCD handle allocation */ if(hpcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if(hpcd->State == HAL_PCD_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); } - + hpcd->State = HAL_PCD_STATE_BUSY; - + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); - + /*Init the Core (common init.) */ USB_CoreInit(hpcd->Instance, hpcd->Init); - + /* Force Device Mode*/ USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); - + /* Init endpoints structures */ for (index = 0; index < 15 ; index++) { @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->IN_ep[index].xfer_buff = 0; hpcd->IN_ep[index].xfer_len = 0; } - + for (index = 0; index < 15 ; index++) { hpcd->OUT_ep[index].is_in = 0; @@ -205,19 +205,19 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->OUT_ep[index].xfer_buff = 0; hpcd->OUT_ep[index].xfer_len = 0; } - + /* Init Device */ USB_DevInit(hpcd->Instance, hpcd->Init); - + hpcd->USB_Address = 0; hpcd->State= HAL_PCD_STATE_READY; - - USB_DevDisconnect (hpcd->Instance); + + USB_DevDisconnect (hpcd->Instance); return HAL_OK; } /** - * @brief DeInitializes the PCD peripheral + * @brief DeInitializes the PCD peripheral * @param hpcd: PCD handle * @retval HAL status */ @@ -228,17 +228,17 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { return HAL_ERROR; } - + hpcd->State = HAL_PCD_STATE_BUSY; - + /* Stop Device */ HAL_PCD_Stop(hpcd); - + /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - + + hpcd->State = HAL_PCD_STATE_RESET; + return HAL_OK; } @@ -274,15 +274,15 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @} */ -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the PCD data + This subsection provides a set of functions allowing to manage the PCD data transfers. @endverbatim @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ +{ __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); USB_StopDevice(hpcd->Instance); @@ -331,7 +331,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0; uint32_t fifoemptymsk = 0, temp = 0; USB_OTG_EPTypeDef *ep = NULL; - + /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { @@ -340,40 +340,40 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { return; } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0; - + /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - + while ( ep_intr ) { if (ep_intr & 0x1) { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - + if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - + HAL_PCD_DataOutStageCallback(hpcd, epnum); } - + if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { /* Inform the upper layer that a setup packet is available */ HAL_PCD_SetupStageCallback(hpcd); CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } - + if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); @@ -383,27 +383,27 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) ep_intr >>= 1; } } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - + epnum = 0; - + while ( ep_intr ) { if (ep_intr & 0x1) /* In ITR */ { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - + if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1 << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - + HAL_PCD_DataInStageCallback(hpcd, epnum); } if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) @@ -431,35 +431,35 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) ep_intr >>= 1; } } - + /* Handle Resume Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) { /* Clear the Remote Wake-up signalling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - + HAL_PCD_ResumeCallback(hpcd); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } - + /* Handle Suspend Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { - + HAL_PCD_SuspendCallback(hpcd); } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - + /* Handle Reset Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; USB_FlushTxFifo(hpcd->Instance , 0 ); - + for (index = 0; index < hpcd->Init.dev_endpoints ; index++) { USBx_INEP(index)->DIEPINT = 0xFF; @@ -467,41 +467,41 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } USBx_DEVICE->DAINT = 0xFFFFFFFF; USBx_DEVICE->DAINTMSK |= 0x10001; - + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - + /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - + /* setup EP0 to receive SETUP packets */ USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } - + /* Handle Enumeration done Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - + hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); - + HAL_PCD_ResetCallback(hpcd); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - + /* Handle RxQLevel Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); temp = USBx->GRXSTSP; ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - + if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { if((temp & USB_OTG_GRXSTSP_BCNT) != 0) @@ -518,40 +518,40 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } - + /* Handle SOF Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { HAL_PCD_SOFCallback(hpcd); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } - + /* Handle Incomplete ISO IN Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } - + /* Handle Incomplete ISO OUT Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } - + /* Handle Connection event Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) { HAL_PCD_ConnectCallback(hpcd); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); } - + /* Handle Disconnection event Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { temp = hpcd->Instance->GOTGINT; - + if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { HAL_PCD_DisconnectCallback(hpcd); @@ -571,7 +571,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { uint32_t wInterrupt_Mask = 0; - + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ @@ -588,34 +588,34 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { + { hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); - + /*set wInterrupt_Mask global variable*/ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /*Set interrupt mask*/ hpcd->Instance->CNTR = wInterrupt_Mask; - + HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) { /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; @@ -627,14 +627,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); HAL_PCD_SOFCallback(hpcd); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) { /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); } } #endif /* USB */ @@ -810,9 +810,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. @endverbatim @@ -866,14 +866,14 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param hpcd: PCD handle * @param ep_addr: endpoint address * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param ep_type: endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep = NULL; - + if ((ep_addr & 0x80) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -883,11 +883,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } ep->num = ep_addr & 0x7F; - + ep->is_in = (0x80 & ep_addr) != 0; ep->maxpacket = ep_mps; ep->type = ep_type; - + __HAL_LOCK(hpcd); USB_ActivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); @@ -901,9 +901,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ +{ PCD_EPTypeDef *ep = NULL; - + if ((ep_addr & 0x80) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -913,9 +913,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } ep->num = ep_addr & 0x7F; - + ep->is_in = (0x80 & ep_addr) != 0; - + __HAL_LOCK(hpcd); USB_DeactivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); @@ -934,18 +934,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep = NULL; - + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0; ep->is_in = 0; ep->num = ep_addr & 0x7F; - + __HAL_LOCK(hpcd); - + if ((ep_addr & 0x7F) == 0 ) { USB_EP0StartXfer(hpcd->Instance , ep); @@ -955,7 +955,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u USB_EPStartXfer(hpcd->Instance , ep); } __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -980,18 +980,18 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep = NULL; - + ep = &hpcd->IN_ep[ep_addr & 0x7F]; - + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0; ep->is_in = 1; ep->num = ep_addr & 0x7F; - + __HAL_LOCK(hpcd); - + if ((ep_addr & 0x7F) == 0 ) { USB_EP0StartXfer(hpcd->Instance , ep); @@ -1000,9 +1000,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance , ep); } - + __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -1015,7 +1015,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1024,19 +1024,19 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { ep = &hpcd->OUT_ep[ep_addr]; } - + ep->is_stall = 1; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + __HAL_LOCK(hpcd); USB_EPSetStall(hpcd->Instance , ep); if((ep_addr & 0x7F) == 0) { USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); } - __HAL_UNLOCK(hpcd); - + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1058,15 +1058,15 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { ep = &hpcd->OUT_ep[ep_addr]; } - + ep->is_stall = 0; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); + + __HAL_LOCK(hpcd); USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1079,7 +1079,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { __HAL_LOCK(hpcd); - + if ((ep_addr & 0x80) == 0x80) { USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); @@ -1088,9 +1088,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_FlushRxFifo(hpcd->Instance); } - - __HAL_UNLOCK(hpcd); - + + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1116,8 +1116,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim @@ -1125,7 +1125,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1159,53 +1159,53 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) * check FIFO for the next packet to be loaded * @param hpcd: PCD handle * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 + * This parameter can be a value from 0 to 15 * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_EPTypeDef *ep = NULL; int32_t len = 0; uint32_t len32b = 0; uint32_t fifoemptymsk = 0; - + ep = &hpcd->IN_ep[epnum]; len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - + len32b = (len + 3) / 4; - + while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } len32b = (len + 3) / 4; - + USB_WritePacket(USBx, ep->xfer_buff, epnum, len); - + ep->xfer_buff += len; ep->xfer_count += len; } - + if(len <= 0) { fifoemptymsk = 0x1 << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - + } - + return HAL_OK; } #endif /* USB_OTG_FS */ @@ -1221,79 +1221,79 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_EPTypeDef *ep = NULL; uint16_t count = 0; uint8_t epindex = 0; - __IO uint16_t wIstr = 0; + __IO uint16_t wIstr = 0; __IO uint16_t wEPVal = 0; - + /* stay in loop while pending interrupts */ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) { /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - + if (epindex == 0) { /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ + + /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0) { /* DIR = 0 */ - + /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; - + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff += ep->xfer_count; - + /* TX COMPLETE */ HAL_PCD_DataInStageCallback(hpcd, 0); - - + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) { hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); hpcd->USB_Address = 0; } - + } else { /* DIR = 1 */ - + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - + if ((wEPVal & USB_EP_SETUP) != 0) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - + USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Process SETUP Packet*/ HAL_PCD_SetupStageCallback(hpcd); } - + else if ((wEPVal & USB_EP_CTR_RX) != 0) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - + if (ep->xfer_count != 0) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); ep->xfer_buff+=ep->xfer_count; } - + /* Process Control Data OUT Packet*/ HAL_PCD_DataOutStageCallback(hpcd, 0); - + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } @@ -1302,15 +1302,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /* Decode and service non control endpoints interrupt */ - + /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); if ((wEPVal & USB_EP_CTR_RX) != 0) - { + { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - + /* OUT double Buffering*/ if (ep->doublebuffer == 0) { @@ -1340,12 +1340,12 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); } /*multi-packet on the NON control OUT endpoint*/ ep->xfer_count+=count; ep->xfer_buff+=count; - + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) { /* RX COMPLETE */ @@ -1355,16 +1355,16 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - + } /* if((wEPVal & EP_CTR_RX) */ - + if ((wEPVal & USB_EP_CTR_TX) != 0) { ep = &hpcd->IN_ep[epindex]; - + /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - + /* IN double Buffering*/ if (ep->doublebuffer == 0) { @@ -1394,12 +1394,12 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); } /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff+=ep->xfer_count; - + /* Zero Length Packet? */ if (ep->xfer_len == 0) { @@ -1410,7 +1410,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - } + } } } return HAL_OK; @@ -1424,7 +1424,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /** * @} */ - + #endif /* STM32F102x6 || STM32F102xB || */ /* STM32F103x6 || STM32F103xB || */ /* STM32F103xE || STM32F103xG || */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c index b34328a..5f3002d 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c @@ -5,10 +5,10 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: - * + Extended features functions: Update FIFO configuration, - * PMA configuration for EPs + * + Extended features functions: Update FIFO configuration, + * PMA configuration for EPs * ****************************************************************************** * @attention @@ -72,7 +72,7 @@ */ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * @verbatim =============================================================================== @@ -98,19 +98,19 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin { uint8_t index = 0; uint32_t Tx_Offset = 0; - + /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - + if(fifo == 0) { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; @@ -122,12 +122,12 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin { Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - + } - + return HAL_OK; } @@ -162,14 +162,14 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) { PCD_EPTypeDef *ep = NULL; - + /* initialize ep structure*/ if ((0x80 & ep_addr) == 0x80) { @@ -179,7 +179,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, { ep = &hpcd->OUT_ep[ep_addr]; } - + /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) { @@ -196,8 +196,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, ep->pmaaddr0 = pmaadress & 0xFFFF; ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; } - - return HAL_OK; + + return HAL_OK; } #endif /* USB */ /** @@ -205,12 +205,12 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, */ /** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions - * @brief Manage device connection state + * @brief Manage device connection state * @{ */ /** - * @brief Software Device Connection, - * this function is not required by USB OTG FS peripheral, it is used + * @brief Software Device Connection, + * this function is not required by USB OTG FS peripheral, it is used * only by USB Device FS peripheral. * @param hpcd: PCD handle * @param state: connection state (0 : disconnected / 1: connected) @@ -223,7 +223,7 @@ __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) UNUSED(state); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCDEx_SetConnectionState could be implemented in the user file - */ + */ } /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c index e178e42..bf00707 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c @@ -9,7 +9,7 @@ * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * ****************************************************************************** * @attention @@ -61,10 +61,10 @@ /** @defgroup PWR_Private_Constants PWR Private Constants * @{ */ - + /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ - */ + */ #define PVD_MODE_IT ((uint32_t)0x00010000) #define PVD_MODE_EVT ((uint32_t)0x00020000) #define PVD_RISING_EDGE ((uint32_t)0x00000001) @@ -76,7 +76,7 @@ /** @defgroup PWR_register_alias_address PWR Register alias address * @{ - */ + */ /* ------------- PWR registers bit address in the alias region ---------------*/ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) #define PWR_CR_OFFSET 0x00 @@ -86,10 +86,10 @@ /** * @} */ - + /** @defgroup PWR_CR_register_alias PWR CR Register alias address * @{ - */ + */ /* --- CR Register ---*/ /* Alias word address of LPSDSR bit */ #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS) @@ -117,7 +117,7 @@ /** * @} */ - + /** * @} */ @@ -147,7 +147,7 @@ static void PWR_OverloadWfe(void) * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -168,7 +168,7 @@ static void PWR_OverloadWfe(void) */ /** - * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @brief Deinitializes the PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) @@ -207,14 +207,14 @@ void HAL_PWR_DisableBkUpAccess(void) * @} */ -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== - + *** PVD configuration *** ========================= [..] @@ -241,12 +241,12 @@ void HAL_PWR_DisableBkUpAccess(void) ===================================== [..] The device features 3 low-power modes: - (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like + (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running (+) Stop mode: All clocks are stopped (+) Standby mode: 1.8V domain powered off - - + + *** Sleep mode *** ================== [..] @@ -255,7 +255,7 @@ void HAL_PWR_DisableBkUpAccess(void) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - + (+) Exit: (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. @@ -268,7 +268,7 @@ void HAL_PWR_DisableBkUpAccess(void) [..] The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. - In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC + In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In Stop mode, all I/O pins keep the same state as in Run mode. @@ -287,27 +287,27 @@ void HAL_PWR_DisableBkUpAccess(void) ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the - Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is - consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also - switched off. SRAM and register contents are lost except for registers in the Backup domain + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is + consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also + switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry - + (+) Entry: (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (+) Exit: - (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in + (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in NRSTpin, IWDG Reset *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, without depending on an external interrupt (Auto-wakeup mode). - + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. *** PWR Workarounds linked to Silicon Limitation *** @@ -316,8 +316,8 @@ void HAL_PWR_DisableBkUpAccess(void) Below the list of all silicon limitations known on STM32F1xx prouct. (#)Workarounds Implemented inside PWR HAL Driver - (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function - + (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function + @endverbatim * @{ */ @@ -339,11 +339,11 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -351,19 +351,19 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); @@ -425,7 +425,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as + * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction @@ -457,14 +457,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) } /** - * @brief Enters Stop mode. + * @brief Enters Stop mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by using an interrupt or a wakeup event, * HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. + * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. + * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON @@ -472,7 +472,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) @@ -481,7 +481,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ + /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ CLEAR_BIT(PWR->CR, PWR_CR_PDDS); /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ @@ -510,7 +510,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /** * @brief Enters Standby mode. * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) + * - Reset pad (still available) * - TAMPER pin if configured for tamper or calibration out. * - WKUP pin (PA0) if enabled. * @retval None @@ -533,11 +533,11 @@ void HAL_PWR_EnterSTANDBYMode(void) /** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -548,9 +548,9 @@ void HAL_PWR_EnableSleepOnExit(void) /** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) @@ -561,8 +561,8 @@ void HAL_PWR_DisableSleepOnExit(void) /** - * @brief Enables CORTEX M3 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -574,9 +574,9 @@ void HAL_PWR_EnableSEVOnPend(void) /** - * @brief Disables CORTEX M3 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) @@ -613,7 +613,7 @@ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c index a862695..e23f65c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c @@ -5,18 +5,18 @@ * @version V1.0.4 * @date 29-April-2016 * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions - * - @verbatim + * + @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] + [..] After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. @@ -26,22 +26,22 @@ [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS) + derived from the System clock (I2S, RTC, ADC, USB OTG FS) ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary - [..] + [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @@ -74,9 +74,9 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -131,10 +131,10 @@ * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -152,19 +152,19 @@ (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System + and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M3 NMI - (Non-Maskable Interrupt) exception vector. + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. - (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x [..] System, AHB and APB buses clocks configuration @@ -179,19 +179,19 @@ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 128. + divided by 128. (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly. This clock is derived of the main PLL through PLL Multiplier. (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK (+@) IWDG clock which is always the LSI clock. (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. - For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. + For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. @endverbatim * @{ */ - + /* Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ @@ -225,16 +225,16 @@ void HAL_RCC_DeInit(void) /* Reset HSEON, CSSON, & PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - + /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - + /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - + /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); - + #if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); @@ -265,19 +265,19 @@ void HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ + + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) @@ -289,14 +289,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { @@ -322,15 +322,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*----------------------------- HSI Configuration --------------------------*/ + /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) { /* When HSI is used as system clock it will not disabled */ @@ -352,10 +352,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -372,10 +372,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { @@ -387,22 +387,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*------------------------------ LSI Configuration -------------------------*/ + /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - + /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) @@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - /* To have a fully stabilized clock in the specified range, a software delay of 1ms + /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ HAL_Delay(1); } @@ -418,11 +418,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ + + /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) @@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*------------------------------ LSE Configuration -------------------------*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { /* Check the parameters */ @@ -440,10 +440,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); @@ -462,8 +462,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -476,8 +476,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ + + /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) { - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -517,13 +517,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { return HAL_ERROR; } - + /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { @@ -532,19 +532,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - + /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); - + /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { @@ -561,11 +561,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ + + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) @@ -585,19 +585,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); - + /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ @@ -629,10 +629,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { @@ -646,11 +646,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ + + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -665,29 +665,29 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_ERROR; } } - + return HAL_OK; } /** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency + * @param FLatency FLASH Latency * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). + * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. + * occur when the clock source will be ready. * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status @@ -695,23 +695,23 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) @@ -728,15 +728,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } - /*------------------------- SYSCLK Configuration ---------------------------*/ + /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { + { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - + /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - /* Check the HSE ready flag */ + /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; @@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - /* Check the PLL ready flag */ + /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; @@ -754,7 +754,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ + /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; @@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Get Start Tick */ tickstart = HAL_GetTick(); - + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) @@ -794,44 +794,44 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_TIMEOUT; } } - } - } + } + } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } - } + } #endif /* FLASH_ACR_LATENCY */ - /*-------------------------- PCLK1 Configuration ---------------------------*/ + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ + + /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } - + /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); - + return HAL_OK; } @@ -842,12 +842,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * - @verbatim + @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @endverbatim @@ -893,7 +893,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; @@ -902,9 +902,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); - + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - + /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } @@ -914,8 +914,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) @@ -933,9 +933,9 @@ void HAL_RCC_DisableCSS(void) } /** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE @@ -949,16 +949,16 @@ void HAL_RCC_DisableCSS(void) * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * + * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -980,9 +980,9 @@ uint32_t HAL_RCC_GetSysClockFreq(void) #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0, pll2mul = 0; #endif /*RCC_CFGR2_PREDIV1SRC*/ - + tmpreg = RCC->CFGR; - + /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { @@ -1016,7 +1016,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul); } - + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) @@ -1047,11 +1047,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ @@ -1061,7 +1061,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency @@ -1070,10 +1070,10 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); -} +} /** - * @brief Returns the PCLK2 frequency + * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency @@ -1082,12 +1082,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); -} +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ @@ -1129,9 +1129,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -1145,7 +1145,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -1155,7 +1155,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) @@ -1184,9 +1184,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Get the RCC_ClkInitStruct according to the internal + * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None @@ -1199,25 +1199,25 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - + #if defined(FLASH_ACR_LATENCY) - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ - *pFLatency = (uint32_t)FLASH_LATENCY_0; + *pFLatency = (uint32_t)FLASH_LATENCY_0; #endif } @@ -1233,7 +1233,7 @@ void HAL_RCC_NMI_IRQHandler(void) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); - + /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } @@ -1247,7 +1247,7 @@ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c index c0cc7d1..7f863f5 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -5,10 +5,10 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -36,8 +36,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -78,22 +78,22 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. - + @endverbatim * @{ */ @@ -104,12 +104,12 @@ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(RTC clock). * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * - * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on + * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to * manually disable it. * @@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ + + /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) { /* check for RTC Parameters used to output RTCCLK */ @@ -133,22 +133,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -165,32 +165,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get timeout */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } - /*------------------------------ ADC clock Configuration ------------------*/ + /*------------------------------ ADC clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); - + /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); } #if defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ I2S2 Configuration ------------------------*/ + /*------------------------------ I2S2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) { /* Check the parameters */ @@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); } - /*------------------------------ I2S3 Configuration ------------------------*/ + /*------------------------------ I2S3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); - + /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); } - /*------------------------------ PLL I2S Configuration ----------------------*/ + /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { @@ -241,13 +241,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); - + /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { @@ -271,12 +271,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ USB clock Configuration ------------------*/ + /*------------------------------ USB clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); - + /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } @@ -288,14 +288,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the PeriphClkInit according to the internal * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t srcclk = 0; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; @@ -410,17 +410,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - + switch (PeriphClk) { #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - case RCC_PERIPHCLK_USB: + case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; - + /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON)) { @@ -448,7 +448,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } - + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) @@ -474,12 +474,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) { - /* Prescaler of 2 selected for USB */ + /* Prescaler of 2 selected for USB */ frequency = pllclk; } else { - /* Prescaler of 3 selected for USB */ + /* Prescaler of 3 selected for USB */ frequency = (2 * pllclk) / 3; } #else @@ -491,7 +491,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - /* Prescaler of 1.5 selected for USB */ + /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif @@ -501,7 +501,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ || defined(STM32F107xC) - case RCC_PERIPHCLK_I2S2: + case RCC_PERIPHCLK_I2S2: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ @@ -552,7 +552,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - case RCC_PERIPHCLK_RTC: + case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; @@ -578,12 +578,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } - case RCC_PERIPHCLK_ADC: + case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2); break; } - default: + default: { break; } @@ -599,10 +599,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function * @brief PLLI2S Management functions * -@verbatim +@verbatim =============================================================================== ##### Extended PLLI2S Management functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the PLLI2S activation or deactivation @@ -641,8 +641,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ + + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) @@ -653,17 +653,17 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); - + /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); - + /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { @@ -699,8 +699,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ + + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) @@ -714,7 +714,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ return HAL_ERROR; } - + return HAL_OK; } @@ -725,10 +725,10 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function * @brief PLL2 Management functions * -@verbatim +@verbatim =============================================================================== ##### Extended PLL2 Management functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the PLL2 activation or deactivation @@ -747,7 +747,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart = 0; - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -771,10 +771,10 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { @@ -783,19 +783,19 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) return HAL_TIMEOUT; } } - + /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); - + /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { @@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) { uint32_t tickstart = 0; - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -833,8 +833,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ + + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c index 938c948..f904f82 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -5,7 +5,7 @@ * @version V1.0.4 * @date 29-April-2016 * @brief TIM HAL module driver - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + Time Base Initialization * + Time Base Start @@ -19,11 +19,11 @@ * + Time Input Capture Initialization * + Time Input Capture Channel Configuration * + Time Input Capture Start - * + Time Input Capture Start Interruption + * + Time Input Capture Start Interruption * + Time Input Capture Start DMA * + Time One Pulse Initialization * + Time One Pulse Channel Configuration - * + Time One Pulse Start + * + Time One Pulse Start * + Time Encoder Interface Initialization * + Time Encoder Interface Start * + Time Encoder Interface Start Interruption @@ -37,18 +37,18 @@ ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output + (++) One-pulse mode output ##### How to use this driver ##### ============================================================================== [..] - (#) Initialize the TIM low level resources by implementing the following functions + (#) Initialize the TIM low level resources by implementing the following functions depending from feature used : (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() @@ -64,21 +64,21 @@ __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - (#) The external Clock can be configured, if needed (the default clock is the + (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before + HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. - (#) Configure the TIM in the desired functioning mode using one of the + (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. @@ -176,10 +176,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @{ */ -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions * -@verbatim +@verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== @@ -220,7 +220,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); } @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM Base peripheral + * @brief DeInitializes the TIM Base peripheral * @param htim : TIM Base handle * @retval HAL status */ @@ -451,10 +451,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions * -@verbatim +@verbatim ============================================================================== ##### Time Output Compare functions ##### ============================================================================== @@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); } @@ -513,7 +513,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM Output Compare handle * @retval HAL status */ @@ -569,13 +569,13 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle + * @param htim : TIM Output Compare handle * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -955,10 +955,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions * -@verbatim +@verbatim ============================================================================== ##### Time PWM functions ##### ============================================================================== @@ -999,7 +999,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); } @@ -1017,7 +1017,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM handle * @retval HAL status */ @@ -1462,10 +1462,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions * -@verbatim +@verbatim ============================================================================== ##### Time Input Capture functions ##### ============================================================================== @@ -1506,7 +1506,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); } @@ -1524,7 +1524,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM Input Capture handle * @retval HAL status */ @@ -1931,10 +1931,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions * -@verbatim +@verbatim ============================================================================== ##### Time One Pulse functions ##### ============================================================================== @@ -1980,7 +1980,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); } @@ -2004,7 +2004,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul } /** - * @brief DeInitializes the TIM One Pulse + * @brief DeInitializes the TIM One Pulse * @param htim : TIM One Pulse handle * @retval HAL status */ @@ -2069,13 +2069,13 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - No need to enable the counter, it's enabled automatically by hardware + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2105,7 +2105,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -2135,13 +2135,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - No need to enable the counter, it's enabled automatically by hardware + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ @@ -2180,10 +2180,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the Capture compare and the Input Capture channels + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2205,10 +2205,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions * -@verbatim +@verbatim ============================================================================== ##### Time Encoder functions ##### ============================================================================== @@ -2260,7 +2260,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); } @@ -2318,7 +2318,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** - * @brief DeInitializes the TIM Encoder interface + * @brief DeInitializes the TIM Encoder interface * @param htim : TIM Encoder handle * @retval HAL status */ @@ -2731,10 +2731,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @} */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management * -@verbatim +@verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== @@ -2881,9 +2881,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) */ /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== @@ -2909,7 +2909,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) @@ -2978,7 +2978,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) @@ -3276,11 +3276,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O } /** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER @@ -3289,13 +3289,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR @@ -3439,7 +3439,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } /** - * @brief Stops the TIM DMA Burst mode + * @brief Stops the TIM DMA Burst mode * @param htim : TIM handle * @param BurstRequestSrc : TIM DMA Request sources to disable * @retval HAL status @@ -3499,11 +3499,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER @@ -3512,13 +3512,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR @@ -3663,7 +3663,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Stop the DMA burst reading + * @brief Stop the DMA burst reading * @param htim : TIM handle * @param BurstRequestSrc : TIM DMA Request sources to disable. * @retval HAL status @@ -3732,7 +3732,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @note TIM6 and TIM7 can only generate an update event. @@ -3776,7 +3776,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) { uint32_t tmpsmcr = 0; @@ -3901,7 +3901,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { uint32_t tmpsmcr = 0; @@ -3939,7 +3939,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3965,7 +3965,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3984,7 +3984,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4104,7 +4104,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * @param htim : TIM handle. * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave + * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ @@ -4139,7 +4139,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI * @param htim: TIM handle. * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave + * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ @@ -4245,9 +4245,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions + * @brief TIM Callbacks functions * -@verbatim +@verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== @@ -4264,7 +4264,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** - * @brief Period elapsed callback in non blocking mode + * @brief Period elapsed callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4278,7 +4278,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** - * @brief Output Compare callback in non blocking mode + * @brief Output Compare callback in non blocking mode * @param htim : TIM OC handle * @retval None */ @@ -4291,7 +4291,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Input Capture callback in non blocking mode + * @brief Input Capture callback in non blocking mode * @param htim : TIM IC handle * @retval None */ @@ -4305,7 +4305,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) } /** - * @brief PWM Pulse finished callback in non blocking mode + * @brief PWM Pulse finished callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4319,7 +4319,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Trigger detection callback in non blocking mode + * @brief Hall Trigger detection callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4333,7 +4333,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) } /** - * @brief Timer error callback in non blocking mode + * @brief Timer error callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4350,15 +4350,15 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permit to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -4438,7 +4438,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) */ /** - * @brief TIM DMA error callback + * @brief TIM DMA error callback * @param hdma : pointer to DMA handle. * @retval None */ @@ -4584,7 +4584,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) TIMx->RCR = Structure->RepetitionCounter; } - /* Generate an update event to reload the Prescaler + /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_EGR_UG; } @@ -5019,8 +5019,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5063,9 +5063,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5098,9 +5098,9 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. @@ -5109,8 +5109,8 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5146,8 +5146,8 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. @@ -5181,8 +5181,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: @@ -5192,8 +5192,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5229,8 +5229,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: @@ -5239,8 +5239,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c index 416dad8..75d4584 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -185,7 +185,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c index 24f343d..1b673cd 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c @@ -6,11 +6,11 @@ * @date 29-April-2016 * @brief USB Low Layer HAL module driver. * - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions * @verbatim @@ -19,7 +19,7 @@ ============================================================================== [..] (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @@ -53,7 +53,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -73,7 +73,7 @@ defined(STM32F103x6) || defined(STM32F103xB) || \ defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) - + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -100,17 +100,17 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. - + @endverbatim * @{ */ - + /*============================================================================== - USB OTG FS peripheral available on STM32F105xx and STM32F107xx devices + USB OTG FS peripheral available on STM32F105xx and STM32F107xx devices ==============================================================================*/ #if defined (USB_OTG_FS) @@ -125,13 +125,13 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - + /* Reset after a PHY select and set Host mode */ USB_CoreReset(USBx); - + /* Deactivate the power down*/ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - + return HAL_OK; } @@ -166,28 +166,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be one of the these values: * @arg USB_DEVICE_MODE: Peripheral mode mode * @arg USB_HOST_MODE: Host mode - * @arg USB_DRD_MODE: Dual Role Device mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) { - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + if ( mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } else if ( mode == USB_DEVICE_MODE) { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } HAL_Delay(50); - + return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains @@ -197,34 +197,34 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeD HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { uint32_t index = 0; - + for (index = 0; index < 15 ; index++) { USBx->DIEPTXF[index] = 0; } - + /*Activate VBUS Sensing B */ USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; /* Restart the Phy Clock */ USBx_PCGCCTL = 0; - + /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - + /* Set Full speed phy */ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); - + /* Flush the FIFOs */ USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ USB_FlushRxFifo(USBx); - + /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0; USBx_DEVICE->DOEPMSK = 0; USBx_DEVICE->DAINT = 0xFFFFFFFF; USBx_DEVICE->DAINTMSK = 0; - + for (index = 0; index < cfg.dev_endpoints; index++) { if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) @@ -235,11 +235,11 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx_INEP(index)->DIEPCTL = 0; } - + USBx_INEP(index)->DIEPTSIZ = 0; USBx_INEP(index)->DIEPINT = 0xFF; } - + for (index = 0; index < cfg.dev_endpoints; index++) { if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) @@ -250,38 +250,38 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx_OUTEP(index)->DOEPCTL = 0; } - + USBx_OUTEP(index)->DOEPTSIZ = 0; USBx_OUTEP(index)->DOEPINT = 0xFF; } - + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - + /* Disable all interrupts. */ USBx->GINTMSK = 0; - + /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFF; - + /* Enable the common interrupts */ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - + /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - + if(cfg.Sof_enable) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - + if (cfg.vbus_sensing_enable == ENABLE) { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } - + return HAL_OK; } @@ -296,9 +296,9 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) { uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - + + USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + do { if (++count > 200000) @@ -307,7 +307,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - + return HAL_OK; } @@ -319,9 +319,9 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - + do { if (++count > 200000) @@ -330,12 +330,12 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - + return HAL_OK; } /** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register + * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. * @param USBx : Selected device * @param speed : device speed @@ -351,7 +351,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) } /** - * @brief USB_GetDevSpeed :Return the Dev Speed + * @brief USB_GetDevSpeed :Return the Dev Speed * @param USBx : Selected device * @retval speed : device speed * This parameter can be one of the these values: @@ -361,7 +361,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { uint8_t speed = 0; - + if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) { @@ -371,7 +371,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { speed = USB_OTG_SPEED_LOW; } - + return speed; } @@ -393,28 +393,28 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy { ep->data_pid_start = 0; } - + if (ep->is_in == 1) { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) { USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) { USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); } } - + return HAL_OK; } @@ -451,16 +451,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { uint16_t pktcnt = 0; - + /* IN endpoint */ if (ep->is_in == 1) { /* Zero Length Packet? */ if (ep->xfer_len == 0) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -470,17 +470,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * exist ? 1 : 0) */ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); } } - + if (ep->type != EP_TYPE_ISOC) { /* Enable the Tx FIFO Empty Interrupt for this EP */ @@ -489,7 +489,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; } } - + if (ep->type == EP_TYPE_ISOC) { if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) @@ -500,11 +500,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe { USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } - } - + } + /* EP enable, IN data in FIFO */ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - + if (ep->type == EP_TYPE_ISOC) { USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len); @@ -516,9 +516,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + if (ep->xfer_len == 0) { USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); @@ -530,7 +530,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); } - + if (ep->type == EP_TYPE_ISOC) { if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) @@ -545,7 +545,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /* EP enable */ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } - + return HAL_OK; } @@ -576,7 +576,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - + if(ep->xfer_len > ep->maxpacket) { ep->xfer_len = ep->maxpacket; @@ -584,15 +584,15 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); } - + /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); } - + /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -602,24 +602,24 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - + if (ep->xfer_len > 0) { ep->xfer_len = ep->maxpacket; } - + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - + /* EP enable */ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -630,7 +630,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { uint32_t count32b = 0 , index = 0; - + count32b = (len + 3) / 4; for (index = 0; index < count32b; index++, src += 4) { @@ -640,7 +640,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -651,11 +651,11 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t index = 0; uint32_t count32b = (len + 3) / 4; - + for ( index = 0; index < count32b; index++, dest += 4 ) { *(__packed uint32_t *)dest = USBx_DFIFO(0); - + } return ((void *)dest); } @@ -663,7 +663,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) @@ -673,7 +673,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) { USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } + } USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else @@ -681,7 +681,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) { USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } + } USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } return HAL_OK; @@ -722,7 +722,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { uint32_t index = 0; - + /* Clear Pending interrupt */ for (index = 0; index < 15 ; index++) { @@ -730,16 +730,16 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) USBx_OUTEP(index)->DOEPINT = 0xFF; } USBx_DEVICE->DAINT = 0xFFFFFFFF; - + /* Clear interrupt masks */ USBx_DEVICE->DIEPMSK = 0; USBx_DEVICE->DOEPMSK = 0; USBx_DEVICE->DAINTMSK = 0; - + /* Flush the FIFO */ USB_FlushRxFifo(USBx); USB_FlushTxFifo(USBx , 0x10 ); - + return HAL_OK; } @@ -754,7 +754,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre { USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD; - + return HAL_OK; } @@ -767,7 +767,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; HAL_Delay(3); - + return HAL_OK; } @@ -780,7 +780,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; HAL_Delay(3); - + return HAL_OK; } @@ -792,7 +792,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg = 0; - + tmpreg = USBx->GINTSTS; tmpreg &= USBx->GINTMSK; return tmpreg; @@ -849,7 +849,7 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { uint32_t tmpreg = 0, msk = 0, emp = 0; - + msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; msk |= ((emp >> epnum) & 0x1) << 7; @@ -873,7 +873,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx : Selected device * @retval return core mode : Host or Device * This parameter can be one of the these values: - * 0 : Host + * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) @@ -890,13 +890,13 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) { /* Set the MPS of the IN EP based on the enumeration speed */ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { USBx_INEP(0)->DIEPCTL |= 3; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - + return HAL_OK; } @@ -912,13 +912,13 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - + return HAL_OK; } /** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode * @param USBx : Selected device * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. @@ -927,81 +927,81 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { uint32_t index = 0; - + /* Restart the Phy Clock */ USBx_PCGCCTL = 0; - + /* no VBUS sensing*/ USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN); USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN); - + /* Disable the FS/LS support mode only */ if((cfg.speed == USB_OTG_SPEED_FULL)&& (USBx != USB_OTG_FS)) { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; } else { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); } - + /* Make sure the FIFOs are flushed. */ USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ USB_FlushRxFifo(USBx); - + /* Clear all pending HC Interrupts */ for (index = 0; index < cfg.Host_channels; index++) { USBx_HC(index)->HCINT = 0xFFFFFFFF; USBx_HC(index)->HCINTMSK = 0; } - + /* Enable VBUS driving */ USB_DriveVbus(USBx, 1); - + HAL_Delay(200); - + /* Disable all interrupts. */ USBx->GINTMSK = 0; - + /* Clear any pending interrupts */ USBx->GINTSTS = 0xFFFFFFFF; - + if(USBx == USB_OTG_FS) { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; + USBx->GRXFSIZ = (uint32_t )0x80; USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); } - + /* Enable the common interrupts */ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - + /* Enable interrupts matching to the Host mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - + return HAL_OK; } /** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval * @param USBx : Selected device * @param freq : clock frequency * This parameter can be one of the these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) { USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - + if (freq == HCFG_48_MHZ) { USBx_HOST->HFIR = (uint32_t)48000; @@ -1023,15 +1023,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; - + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); return HAL_OK; } @@ -1039,18 +1039,18 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * @brief USB_DriveVbus : activate or de-activate vbus * @param state : VBUS state * This parameter can be one of the these values: - * 0 : VBUS Active + * 0 : VBUS Active * 1 : VBUS Inactive * @retval HAL status */ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) { USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); @@ -1073,7 +1073,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); } @@ -1111,7 +1111,7 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -1121,9 +1121,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, { /* Clear old interrupt conditions for this host channel. */ USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - + /* Enable channel interrupts required for this transfer. */ - switch (ep_type) + switch (ep_type) { case EP_TYPE_CTRL: case EP_TYPE_BULK: @@ -1133,13 +1133,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCINTMSK_DTERRM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } break; - + case EP_TYPE_INTR: USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ USB_OTG_HCINTMSK_STALLM |\ @@ -1148,33 +1148,33 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCINTMSK_NAKM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } - + break; - + case EP_TYPE_ISOC: USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ USB_OTG_HCINTMSK_ACKM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); } break; } - + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= (1 << ch_num); - + /* Make sure host channel interrupts are enabled. */ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - + /* Program the HCCHAR register */ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ @@ -1182,12 +1182,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ (mps & USB_OTG_HCCHAR_MPSIZ)); - + if (ep_type == EP_TYPE_INTR) { USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; } - + return HAL_OK; } @@ -1209,12 +1209,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint16_t num_packets = 0; uint16_t max_hc_pkt_count = 256; uint32_t tmpreg = 0; - + /* Compute the expected number of packets associated to the transfer */ if (hc->xfer_len > 0) { num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - + if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; @@ -1229,31 +1229,31 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe { hc->xfer_len = num_packets * hc->max_packet; } - + /* Initialize the HCTSIZn register */ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - + is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - + /* Set host channel enable */ tmpreg = USBx_HC(hc->ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - + if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) { - switch(hc->ep_type) + switch(hc->ep_type) { /* Non periodic transfer */ case EP_TYPE_CTRL: case EP_TYPE_BULK: len_words = (hc->xfer_len + 3) / 4; - + /* check if there is enough space in FIFO space */ if(len_words > (USBx->HNPTXSTS & 0xFFFF)) { @@ -1261,7 +1261,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; } break; - + /* Periodic transfer */ case EP_TYPE_INTR: case EP_TYPE_ISOC: @@ -1270,18 +1270,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ { /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; } break; - + default: break; } - + /* Write packet into the Tx FIFO. */ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len); } - + return HAL_OK; } @@ -1305,12 +1305,12 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { uint32_t count = 0; - + /* Check for space in the request queue to issue the halt. */ if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - + if ((USBx->HNPTXSTS & 0xFFFF) == 0) { USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { break; } - } + } while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else @@ -1333,7 +1333,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) else { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - + if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) { USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; @@ -1345,15 +1345,15 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { break; } - } + } while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } - + return HAL_OK; } @@ -1368,17 +1368,17 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) { uint8_t num_packets = 1; uint32_t tmpreg = 0; - + USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ USB_OTG_HCTSIZ_DOPING; - + /* Set host channel enable */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; + + return HAL_OK; } /** @@ -1391,13 +1391,13 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) uint8_t index; uint32_t count = 0; uint32_t value = 0; - + USB_DisableGlobalInt(USBx); - + /* Flush FIFO */ USB_FlushTxFifo(USBx, 0x10); USB_FlushRxFifo(USBx); - + /* Flush out any leftover queued requests. */ for (index = 0; index <= 15; index++) { @@ -1407,7 +1407,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) value &= ~USB_OTG_HCCHAR_EPDIR; USBx_HC(index)->HCCHAR = value; } - + /* Halt all channels to put them into a known state. */ for (index = 0; index <= 15; index++) { @@ -1416,7 +1416,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; USBx_HC(index)->HCCHAR = value; - + do { if (++count > 1000) @@ -1426,12 +1426,12 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } - + /* Clear any pending Host interrupts */ USBx_HOST->HAINT = 0xFFFFFFFF; USBx->GINTSTS = 0xFFFFFFFF; USB_EnableGlobalInt(USBx); - + return HAL_OK; } @@ -1465,7 +1465,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) #endif /* USB_OTG_FS */ /*============================================================================== - USB Device FS peripheral available on STM32F102xx and STM32F103xx devices + USB Device FS peripheral available on STM32F102xx and STM32F103xx devices ==============================================================================*/ #if defined (USB) /** @@ -1477,7 +1477,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1493,14 +1493,14 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { uint32_t winterruptmask = 0; - + /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /* Set interrupt mask */ USBx->CNTR |= winterruptmask; - + return HAL_OK; } @@ -1513,14 +1513,14 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { uint32_t winterruptmask = 0; - + /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /* Clear interrupt mask */ USBx->CNTR &= ~winterruptmask; - + return HAL_OK; } @@ -1534,7 +1534,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1542,7 +1542,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit : Initializes the USB controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_CfgTypeDef structure that contains @@ -1550,20 +1550,20 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) * @retval HAL status */ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ +{ /* Init Device */ /*CNTR_FRES = 1*/ USBx->CNTR = USB_CNTR_FRES; - + /*CNTR_FRES = 0*/ USBx->CNTR = 0; - + /*Clear pending interrupts*/ USBx->ISTR = 0; - + /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - + return HAL_OK; } @@ -1577,7 +1577,7 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1591,7 +1591,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1623,11 +1623,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) break; default: break; - } - + } + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) + + if (ep->doublebuffer == 0) { if (ep->is_in) { @@ -1635,7 +1635,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } else { @@ -1655,16 +1655,16 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_DBUF(USBx, ep->num); /*Set buffer address for double buffered mode*/ PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - + if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -1679,7 +1679,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -1691,13 +1691,13 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { if (ep->is_in) { PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { @@ -1708,16 +1708,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /*Double Buffer*/ else - { + { if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -1732,7 +1732,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -1746,7 +1746,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) { uint16_t pmabuffer = 0; uint32_t len = ep->xfer_len; - + /* IN endpoint */ if (ep->is_in == 1) { @@ -1754,16 +1754,16 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len=ep->maxpacket; - ep->xfer_len-=len; + ep->xfer_len-=len; } else - { + { len=ep->xfer_len; ep->xfer_len =0; } - + /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); PCD_SET_EP_TX_CNT(USBx, ep->num, len); @@ -1786,7 +1786,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } - + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ @@ -1795,16 +1795,16 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len=ep->maxpacket; - ep->xfer_len-=len; + ep->xfer_len-=len; } else { len=ep->xfer_len; ep->xfer_len =0; } - + /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); @@ -1814,15 +1814,15 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) /*Set the Double buffer counter*/ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); } - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -1832,7 +1832,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1840,7 +1840,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -1849,7 +1849,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep */ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1859,21 +1859,21 @@ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) { if (ep->num == 0) { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); } else { if (ep->is_in) { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); } else { @@ -1913,13 +1913,13 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ USBx->CNTR = USB_CNTR_FRES; - + /* clear interrupt status register */ USBx->ISTR = 0; - + /* switch-off device */ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - + return HAL_OK; } @@ -1932,12 +1932,12 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) { - if(address == 0) + if(address == 0) { /* set device address and enable function */ USBx->DADDR = USB_DADDR_EF; } - + return HAL_OK; } @@ -1948,7 +1948,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) */ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1977,7 +1977,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) { uint32_t tmpreg = 0; - + tmpreg = USBx->ISTR; return tmpreg; } @@ -1989,7 +1989,7 @@ uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2003,7 +2003,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2019,7 +2019,7 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2035,7 +2035,7 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2050,7 +2050,7 @@ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2064,7 +2064,7 @@ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2079,7 +2079,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR |= USB_CNTR_RESUME; - + return HAL_OK; } @@ -2107,7 +2107,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui uint32_t nbytes = (wNBytes + 1) >> 1; /* nbytes = (wNBytes + 1) / 2 */ uint32_t index = 0, temp1 = 0, temp2 = 0; uint16_t *pdwVal = NULL; - + pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); for (index = nbytes; index != 0; index--) { @@ -2133,7 +2133,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin uint32_t nbytes = (wNBytes + 1) >> 1;/* /2*/ uint32_t index = 0; uint32_t *pdwVal = NULL; - + pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); for (index = nbytes; index != 0; index--) { @@ -2163,7 +2163,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + /* Wait for AHB master IDLE state. */ do { @@ -2173,11 +2173,11 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - + /* Core Soft Reset */ count = 0; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - + do { if (++count > 200000) @@ -2186,7 +2186,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - + return HAL_OK; } /** |