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authorTrygve Laugstøl <trygvis@inamo.no>2017-12-07 12:12:59 +0100
committerTrygve Laugstøl <trygvis@inamo.no>2017-12-07 12:13:50 +0100
commit1fba999bec5a589e4785594fb1a6fbfab9129097 (patch)
tree1ff18f14284f89fa8bee1bd123802c4f40fec4be /test/kicad_pcb/parser-1.kicad_pcb
parentaa7e1cac11f04f997317c5263b00d1e7d0b94608 (diff)
downloadee-python-1fba999bec5a589e4785594fb1a6fbfab9129097.tar.gz
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o A start of a kicad_pcb parser.
Diffstat (limited to 'test/kicad_pcb/parser-1.kicad_pcb')
-rw-r--r--test/kicad_pcb/parser-1.kicad_pcb335
1 files changed, 335 insertions, 0 deletions
diff --git a/test/kicad_pcb/parser-1.kicad_pcb b/test/kicad_pcb/parser-1.kicad_pcb
new file mode 100644
index 0000000..b8efabc
--- /dev/null
+++ b/test/kicad_pcb/parser-1.kicad_pcb
@@ -0,0 +1,335 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.7+dfsg1-1)
+
+ (general
+ (links 5)
+ (no_connects 0)
+ (area 139.649999 101.549999 152.450001 109.270001)
+ (thickness 1.6)
+ (drawings 5)
+ (tracks 14)
+ (zones 0)
+ (modules 4)
+ (nets 4)
+ )
+
+ (page A4)
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ (45 Margin user)
+ (46 B.CrtYd user)
+ (47 F.CrtYd user)
+ (48 B.Fab user)
+ (49 F.Fab user)
+ )
+
+ (setup
+ (last_trace_width 0.25)
+ (trace_clearance 0.2)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.2)
+ (segment_width 0.2)
+ (edge_width 0.2)
+ (via_size 0.6)
+ (via_drill 0.4)
+ (via_min_size 0.4)
+ (via_min_drill 0.3)
+ (uvia_size 0.3)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.2)
+ (uvia_min_drill 0.1)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.524 1.524)
+ (pad_drill 0.762)
+ (pad_to_mask_clearance 0.2)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFF7F)
+ (pcbplotparams
+ (layerselection 0x00030_80000001)
+ (usegerberextensions false)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 "Net-(C1-Pad1)")
+ (net 2 "Net-(J1-Pad2)")
+ (net 3 GND)
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.25)
+ (via_dia 0.6)
+ (via_drill 0.4)
+ (uvia_dia 0.3)
+ (uvia_drill 0.1)
+ (add_net GND)
+ (add_net "Net-(C1-Pad1)")
+ (add_net "Net-(J1-Pad2)")
+ )
+
+ (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 59958EE7) (tstamp 5A29152D)
+ (at 149.86 106.68 180)
+ (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
+ (tags "capacitor 0603")
+ (path /5A2915AE)
+ (attr smd)
+ (fp_text reference C1 (at 0 -1.5 180) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value C (at 0 1.5 180) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start 1.4 0.65) (end -1.4 0.65) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.4 0.65) (end 1.4 -0.65) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.4 -0.65) (end -1.4 0.65) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.4 -0.65) (end 1.4 -0.65) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12))
+ (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12))
+ (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
+ (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
+ (fp_text user %R (at 0 0 180) (layer F.Fab)
+ (effects (font (size 0.3 0.3) (thickness 0.075)))
+ )
+ (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
+ (net 3 GND))
+ (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
+ (net 1 "Net-(C1-Pad1)"))
+ (model Capacitors_SMD.3dshapes/C_0603.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5A291533)
+ (at 142.24 106.68 180)
+ (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+ (tags "Through hole pin header THT 1x02 2.54mm single row")
+ (path /5A2914CA)
+ (fp_text reference J1 (at 0 -2.33 180) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Conn_01x02 (at 0 4.87 180) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+ (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+ (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+ (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+ (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_text user %R (at 0 1.27 270) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 3 GND))
+ (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 2 "Net-(J1-Pad2)"))
+ (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Resistors_SMD:R_0603 (layer F.Cu) (tedit 58E0A804) (tstamp 5A291539)
+ (at 146.05 104.14)
+ (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
+ (tags "resistor 0603")
+ (path /5A29147F)
+ (attr smd)
+ (fp_text reference R1 (at 0 -1.45) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value R (at 0 1.5) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user %R (at 0 0) (layer F.Fab)
+ (effects (font (size 0.4 0.4) (thickness 0.075)))
+ )
+ (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
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+ (fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
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+ (fp_line (start -1.25 -0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.25 0.7) (end 1.25 -0.7) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.25 0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+ (pad 1 smd rect (at -0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+ (net 2 "Net-(J1-Pad2)"))
+ (pad 2 smd rect (at 0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+ (net 1 "Net-(C1-Pad1)"))
+ (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Resistors_SMD:R_0603 (layer F.Cu) (tedit 58E0A804) (tstamp 5A29153F)
+ (at 146.05 106.68 180)
+ (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
+ (tags "resistor 0603")
+ (path /5A29151D)
+ (attr smd)
+ (fp_text reference R2 (at 0 -1.45 180) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value R (at 0 1.5 180) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user %R (at 0 0 180) (layer F.Fab)
+ (effects (font (size 0.4 0.4) (thickness 0.075)))
+ )
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+ (fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
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+ (fp_line (start 1.25 0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+ (pad 1 smd rect (at -0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+ (net 1 "Net-(C1-Pad1)"))
+ (pad 2 smd rect (at 0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+ (net 3 GND))
+ (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (dimension 12.7 (width 0.3) (layer Dwgs.User)
+ (gr_text "12,700 mm" (at 146.05 97.71) (layer Dwgs.User)
+ (effects (font (size 1.5 1.5) (thickness 0.3)))
+ )
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