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author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:20:28 +0200 |
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committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:20:28 +0200 |
commit | 77af3b8b331d4a67a3523f03081b1e2a98915a0a (patch) | |
tree | 20c6411625d8e01b6aa752e70d603cd736472740 /Artix-7/mw.j2 | |
parent | bf86cf7a2b58e581a46f6016776c24ccb8bd61ac (diff) | |
download | semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.gz semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.bz2 semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.xz semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.zip |
o Using 'Has hard core' record property for a few values.
Diffstat (limited to 'Artix-7/mw.j2')
-rw-r--r-- | Artix-7/mw.j2 | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/Artix-7/mw.j2 b/Artix-7/mw.j2 index 5fce575..79768db 100644 --- a/Artix-7/mw.j2 +++ b/Artix-7/mw.j2 @@ -1,5 +1,7 @@ = {{ part["Part number"] }} = +== Overview == + {|class='wikitable' !Part number |[[Part number::{{ part["Part number"] }}]] @@ -13,38 +15,42 @@ !Distributed RAM |[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]] |- -!DSP48E1 Slices -|[[DSP48E1 Slices::{{ part["DSP48E1 Slices"] }}]] -|- !RAM blocks |[[RAM blocks::{{ part["36 Kb"] }}]] |- -!RAM +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM |[[RAM::{{ part["Max (Kb)"] }} kB]] |- !Clock management tiles |[[Xilix clock management tiles::{{ part["CMTs"] }}]] |- -!PCIe -|[[PCIe::{{ part["PCIe"] }}]] -|- -!GTPs -|[[GTPs::{{ part["GTPs"] }}]] -|- -!XADC Blocks -|[[XADC Blocks::{{ part["XADC Blocks"] }}]] -|- -!IO banks -|[[IO banks::{{ part["Total I/O Banks"] }}]] -|- !Available IO |[[Available IO::{{ part["Max User I/O"] }}]] |- -!RAM block size -|[[RAM block size::36 kB]] +!IO banks +|[[IO banks::{{ part["Total I/O Banks"] }}]] |- |} +== Hard cores == + +{% if part["GTPs"] %} +* [[Has hard core::Gigabit transceiver;{{ part["GTPs"] }}]] +{% endif %} +{% if part["PCIe"] %} +* [[Has hard core::PCIe;{{ part["PCIe"] }}]] +* [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]] +{% endif %} +{% if part["XADC Blocks"] %} +* [[Has hard core::XADC;{{ part["XADC Blocks"] }}]] +{% endif %} +{% if part["DSP48E1 Slices"] %} +* [[Has hard core::DSP48E1 slice;{{ part["DSP48E1 Slices"] }}]] +{% endif %} + [[Category:Generated]] [[Category:FPGA Chip]] [[Category:Artix-7 generated data set]] |