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| author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 20:46:09 +0200 |
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| committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 20:46:09 +0200 |
| commit | 07a64e370e06603c9702e93e6b54540b320c2cda (patch) | |
| tree | 463a5293b81684e7907a38237e89529b0db8e1eb /Artix-7/mw/XC7A50T.mw | |
| download | semantic-sandbox-07a64e370e06603c9702e93e6b54540b320c2cda.tar.gz semantic-sandbox-07a64e370e06603c9702e93e6b54540b320c2cda.tar.bz2 semantic-sandbox-07a64e370e06603c9702e93e6b54540b320c2cda.tar.xz semantic-sandbox-07a64e370e06603c9702e93e6b54540b320c2cda.zip | |
o Generating mediawiki pages from Artix-7 docs.
Diffstat (limited to 'Artix-7/mw/XC7A50T.mw')
| -rw-r--r-- | Artix-7/mw/XC7A50T.mw | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw new file mode 100644 index 0000000..15b72e2 --- /dev/null +++ b/Artix-7/mw/XC7A50T.mw @@ -0,0 +1,53 @@ += XC7A50T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A50T]] +|- +!Logic Cells +|[[Xilix logic cells::52160]] +|- +!Slices +|[[Slices::8150]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::600]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::120]] +|- +!18 Kb +|[[18 Kb::150]] +|- +!RAM blocks +|[[RAM blocks::75]] +|- +!Max +|[[Max::2700]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::5]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::4]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::5]] +|- +!Max User I/O +|[[Max User I/O::250]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] |