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author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:20:28 +0200 |
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committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:20:28 +0200 |
commit | 77af3b8b331d4a67a3523f03081b1e2a98915a0a (patch) | |
tree | 20c6411625d8e01b6aa752e70d603cd736472740 /Artix-7/mw/XC7A50T.mw | |
parent | bf86cf7a2b58e581a46f6016776c24ccb8bd61ac (diff) | |
download | semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.gz semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.bz2 semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.tar.xz semantic-sandbox-77af3b8b331d4a67a3523f03081b1e2a98915a0a.zip |
o Using 'Has hard core' record property for a few values.
Diffstat (limited to 'Artix-7/mw/XC7A50T.mw')
-rw-r--r-- | Artix-7/mw/XC7A50T.mw | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw index 2cc79d3..79889ee 100644 --- a/Artix-7/mw/XC7A50T.mw +++ b/Artix-7/mw/XC7A50T.mw @@ -1,5 +1,7 @@ = XC7A50T = +== Overview == + {|class='wikitable' !Part number |[[Part number::XC7A50T]] @@ -13,38 +15,34 @@ !Distributed RAM |[[Distributed RAM::600 kB]] |- -!DSP48E1 Slices -|[[DSP48E1 Slices::120]] -|- !RAM blocks |[[RAM blocks::75]] |- -!RAM +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM |[[RAM::2700 kB]] |- !Clock management tiles |[[Xilix clock management tiles::5]] |- -!PCIe -|[[PCIe::1]] -|- -!GTPs -|[[GTPs::4]] -|- -!XADC Blocks -|[[XADC Blocks::1]] -|- -!IO banks -|[[IO banks::5]] -|- !Available IO |[[Available IO::250]] |- -!RAM block size -|[[RAM block size::36 kB]] +!IO banks +|[[IO banks::5]] |- |} +== Hard cores == + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;120]] + [[Category:Generated]] [[Category:FPGA Chip]] [[Category:Artix-7 generated data set]] |