o Using 'Has hard core' record property for a few values.

8 files changed, 128 insertions, 144 deletions

diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw
index 27810fe..4b6cea2 100644
--- a/Artix-7/mw/XC7A100T.mw
+++ b/Artix-7/mw/XC7A100T.mw
@@ -1,5 +1,7 @@
 = XC7A100T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A100T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::1188 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::240]]
-|-
 !RAM blocks
 |[[RAM blocks::135]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::4860 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::6]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::8]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::6]]
-|-
 !Available IO
 |[[Available IO::300]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::6]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;8]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;240]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
index 726ccf7..30e4757 100644
--- a/Artix-7/mw/XC7A12T.mw
+++ b/Artix-7/mw/XC7A12T.mw
@@ -1,5 +1,7 @@
 = XC7A12T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A12T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::171 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::40]]
-|-
 !RAM blocks
 |[[RAM blocks::20]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::720 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::3]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::2]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::3]]
-|-
 !Available IO
 |[[Available IO::150]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::3]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;2]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;40]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw
index 200befb..36f1746 100644
--- a/Artix-7/mw/XC7A15T.mw
+++ b/Artix-7/mw/XC7A15T.mw
@@ -1,5 +1,7 @@
 = XC7A15T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A15T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::200 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::45]]
-|-
 !RAM blocks
 |[[RAM blocks::25]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::900 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::5]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::4]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::5]]
-|-
 !Available IO
 |[[Available IO::250]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::5]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;4]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;45]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw
index 887a4d4..fd9eca7 100644
--- a/Artix-7/mw/XC7A200T.mw
+++ b/Artix-7/mw/XC7A200T.mw
@@ -1,5 +1,7 @@
 = XC7A200T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A200T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::2888 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::740]]
-|-
 !RAM blocks
 |[[RAM blocks::365]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::13140 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::10]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::16]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::10]]
-|-
 !Available IO
 |[[Available IO::500]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::10]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;16]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;740]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw
index 5730d02..a97549a 100644
--- a/Artix-7/mw/XC7A25T.mw
+++ b/Artix-7/mw/XC7A25T.mw
@@ -1,5 +1,7 @@
 = XC7A25T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A25T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::313 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::80]]
-|-
 !RAM blocks
 |[[RAM blocks::45]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::1620 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::3]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::4]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::3]]
-|-
 !Available IO
 |[[Available IO::150]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::3]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;4]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;80]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw
index 0be1dad..072ffae 100644
--- a/Artix-7/mw/XC7A35T.mw
+++ b/Artix-7/mw/XC7A35T.mw
@@ -1,5 +1,7 @@
 = XC7A35T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A35T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::400 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::90]]
-|-
 !RAM blocks
 |[[RAM blocks::50]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::1800 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::5]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::4]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::5]]
-|-
 !Available IO
 |[[Available IO::250]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::5]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;4]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;90]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw
index 2cc79d3..79889ee 100644
--- a/Artix-7/mw/XC7A50T.mw
+++ b/Artix-7/mw/XC7A50T.mw
@@ -1,5 +1,7 @@
 = XC7A50T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A50T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::600 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::120]]
-|-
 !RAM blocks
 |[[RAM blocks::75]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::2700 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::5]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::4]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::5]]
-|-
 !Available IO
 |[[Available IO::250]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::5]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;4]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;120]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw
index 6d3aed5..c014925 100644
--- a/Artix-7/mw/XC7A75T.mw
+++ b/Artix-7/mw/XC7A75T.mw
@@ -1,5 +1,7 @@
 = XC7A75T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A75T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::892 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::180]]
-|-
 !RAM blocks
 |[[RAM blocks::105]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::3780 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::6]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::8]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::6]]
-|-
 !Available IO
 |[[Available IO::300]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::6]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;8]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;180]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]