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Diffstat (limited to 'Kintex-7/mw.j2')
| -rw-r--r-- | Kintex-7/mw.j2 | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/Kintex-7/mw.j2 b/Kintex-7/mw.j2 new file mode 100644 index 0000000..01f80ef --- /dev/null +++ b/Kintex-7/mw.j2 @@ -0,0 +1,54 @@ += Overview = + +[[Part number::{{ part["Part number"] }}]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::{{ part["Logic Cells"] }}]] +|- +!Slices +|[[Xilix 7 series slices::{{ part["Slices"] }}]] +|- +!Distributed RAM +|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]] +|- +!RAM blocks +|[[RAM blocks::{{ part["36 Kb"] }}]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::{{ part["Max (Kb)"] }} kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::{{ part["CMTs"] }}]] +|- +!Available IO +|[[Available IO::{{ part["Max User I/O"] }}]] +|- +!IO banks +|[[IO banks::{{ part["Total I/O Banks"] }}]] +|- +|} + += Hard cores = + +{% if part["GTXs"] %} +* [[Has hard core::Gigabit transceiver;{{ part["GTXs"] }}]] +{% endif %} +{% if part["PCIe"] %} +* [[Has hard core::PCIe;{{ part["PCIe"] }}]] +* [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]] +{% endif %} +{% if part["XADC Blocks"] %} +* [[Has hard core::XADC;{{ part["XADC Blocks"] }}]] +{% endif %} +{% if part["DSP48E1 Slices"] %} +* [[Has hard core::DSP48E1 slice;{{ part["DSP48E1 Slices"] }}]] +{% endif %} + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] + |