diff options
Diffstat (limited to 'Kintex-7')
| -rw-r--r-- | Kintex-7/Kintex-7.ods | bin | 0 -> 18506 bytes | |||
| -rw-r--r-- | Kintex-7/mw.j2 | 54 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K160T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K325T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K355T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K410T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K420T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K480T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K70T.mw | 43 | ||||
| -rw-r--r-- | Kintex-7/part-packages.csv | 22 | ||||
| -rw-r--r-- | Kintex-7/parts.csv | 27 | ||||
| -rwxr-xr-x | Kintex-7/run.py | 129 |
12 files changed, 533 insertions, 0 deletions
diff --git a/Kintex-7/Kintex-7.ods b/Kintex-7/Kintex-7.ods Binary files differnew file mode 100644 index 0000000..9a883f2 --- /dev/null +++ b/Kintex-7/Kintex-7.ods diff --git a/Kintex-7/mw.j2 b/Kintex-7/mw.j2 new file mode 100644 index 0000000..01f80ef --- /dev/null +++ b/Kintex-7/mw.j2 @@ -0,0 +1,54 @@ += Overview = + +[[Part number::{{ part["Part number"] }}]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::{{ part["Logic Cells"] }}]] +|- +!Slices +|[[Xilix 7 series slices::{{ part["Slices"] }}]] +|- +!Distributed RAM +|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]] +|- +!RAM blocks +|[[RAM blocks::{{ part["36 Kb"] }}]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::{{ part["Max (Kb)"] }} kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::{{ part["CMTs"] }}]] +|- +!Available IO +|[[Available IO::{{ part["Max User I/O"] }}]] +|- +!IO banks +|[[IO banks::{{ part["Total I/O Banks"] }}]] +|- +|} + += Hard cores = + +{% if part["GTXs"] %} +* [[Has hard core::Gigabit transceiver;{{ part["GTXs"] }}]] +{% endif %} +{% if part["PCIe"] %} +* [[Has hard core::PCIe;{{ part["PCIe"] }}]] +* [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]] +{% endif %} +{% if part["XADC Blocks"] %} +* [[Has hard core::XADC;{{ part["XADC Blocks"] }}]] +{% endif %} +{% if part["DSP48E1 Slices"] %} +* [[Has hard core::DSP48E1 slice;{{ part["DSP48E1 Slices"] }}]] +{% endif %} + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] + diff --git a/Kintex-7/mw/Chip:XC7K160T.mw b/Kintex-7/mw/Chip:XC7K160T.mw new file mode 100644 index 0000000..0698263 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K160T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::162240]] +|- +!Slices +|[[Xilix 7 series slices::25350]] +|- +!Distributed RAM +|[[Distributed RAM::2188 kB]] +|- +!RAM blocks +|[[RAM blocks::325]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::11700 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::8]] +|- +!Available IO +|[[Available IO::400]] +|- +!IO banks +|[[IO banks::8]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;8]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K325T.mw b/Kintex-7/mw/Chip:XC7K325T.mw new file mode 100644 index 0000000..bcd44c6 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K325T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::326080]] +|- +!Slices +|[[Xilix 7 series slices::50950]] +|- +!Distributed RAM +|[[Distributed RAM::4000 kB]] +|- +!RAM blocks +|[[RAM blocks::445]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::16020 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::10]] +|- +!Available IO +|[[Available IO::500]] +|- +!IO banks +|[[IO banks::10]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;16]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K355T.mw b/Kintex-7/mw/Chip:XC7K355T.mw new file mode 100644 index 0000000..1043a31 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K355T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::356160]] +|- +!Slices +|[[Xilix 7 series slices::55650]] +|- +!Distributed RAM +|[[Distributed RAM::5088 kB]] +|- +!RAM blocks +|[[RAM blocks::715]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::25740 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::6]] +|- +!Available IO +|[[Available IO::300]] +|- +!IO banks +|[[IO banks::6]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;24]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K410T.mw b/Kintex-7/mw/Chip:XC7K410T.mw new file mode 100644 index 0000000..733e056 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K410T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::406720]] +|- +!Slices +|[[Xilix 7 series slices::63550]] +|- +!Distributed RAM +|[[Distributed RAM::5663 kB]] +|- +!RAM blocks +|[[RAM blocks::795]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::28620 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::10]] +|- +!Available IO +|[[Available IO::500]] +|- +!IO banks +|[[IO banks::10]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;16]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K420T.mw b/Kintex-7/mw/Chip:XC7K420T.mw new file mode 100644 index 0000000..dc59e81 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K420T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::416960]] +|- +!Slices +|[[Xilix 7 series slices::65150]] +|- +!Distributed RAM +|[[Distributed RAM::5938 kB]] +|- +!RAM blocks +|[[RAM blocks::835]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::30060 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::8]] +|- +!Available IO +|[[Available IO::400]] +|- +!IO banks +|[[IO banks::8]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;32]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw new file mode 100644 index 0000000..b5a1bf3 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K480T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::477760]] +|- +!Slices +|[[Xilix 7 series slices::74650]] +|- +!Distributed RAM +|[[Distributed RAM::6788 kB]] +|- +!RAM blocks +|[[RAM blocks::955]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::34380 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::8]] +|- +!Available IO +|[[Available IO::400]] +|- +!IO banks +|[[IO banks::8]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;32]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/mw/Chip:XC7K70T.mw b/Kintex-7/mw/Chip:XC7K70T.mw new file mode 100644 index 0000000..206e1bc --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K70T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::65600]] +|- +!Slices +|[[Xilix 7 series slices::10250]] +|- +!Distributed RAM +|[[Distributed RAM::838 kB]] +|- +!RAM blocks +|[[RAM blocks::135]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::4860 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::6]] +|- +!Available IO +|[[Available IO::300]] +|- +!IO banks +|[[IO banks::6]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;8]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] diff --git a/Kintex-7/part-packages.csv b/Kintex-7/part-packages.csv new file mode 100644 index 0000000..1e94523 --- /dev/null +++ b/Kintex-7/part-packages.csv @@ -0,0 +1,22 @@ +#,Table 7: Kintex-7 FPGA Device-Package Combinations and Maximum I/Os,,,,,,,,,,,,,,,,,,,, +Package (1),FBG484,,,FBG676 (2),,,FFG676 (2),,,FBG900 (3),,,FFG900 (3),,,FFG901,,,FFG1156,, +Size (mm),23,,,27,,,27,,,31,,,31,,,31,,,35,, +Ball pitch (mm),1.0,,,1.0,,,1.0,,,1.0,,,1.0,,,1.0,,,1.0,, +,,IO,,,IO,,,IO,,,IO,,,IO,,,IO,,,IO, +,GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6),GTX(4),HR(5),HP(6) +XC7K70T,4,185,100,8,200,100,,,,,,,,,,,,,,, +XC7K160T,4,185,100,8,250,150,8,250,150,,,,,,,,,,,, +XC7K325T,,,,8,250,150,8,250,150,16,350,150,16,350,150,,,,,, +XC7K355T,,,,,,,,,,,,,,,,24,300,0,,, +XC7K410T,,,,8,250,150,8,250,150,16,350,150,16,350,150,,,,,, +XC7K420T,,,,,,,,,,,,,,,,28,380,0,32,400,0 +XC7K480T,,,,,,,,,,,,,,,,28,380,0,32,400,0 +,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,, +#,Notes: ,,,,,,,,,,,,,,,,,,,, +#,"1. All packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb option. ",,,,,,,,,,,,,,,,,,,, +#,2. Devices in FBG676 and FFG676 are footprint compatible. ,,,,,,,,,,,,,,,,,,,, +#,3. Devices in FBG900 and FFG900 are footprint compatible. ,,,,,,,,,,,,,,,,,,,, +#,4. GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. Refer to Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) for details. ,,,,,,,,,,,,,,,,,,,, +#,5. HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V. ,,,,,,,,,,,,,,,,,,,, +#,6. HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V. ,,,,,,,,,,,,,,,,,,,, diff --git a/Kintex-7/parts.csv b/Kintex-7/parts.csv new file mode 100644 index 0000000..0171f3d --- /dev/null +++ b/Kintex-7/parts.csv @@ -0,0 +1,27 @@ +#,Table 6: Kintex-7 FPGA Feature Summary by Device,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +#,,Configurable Logic Blocks (CLBs),,,Block RAM Blocks(3),,,,,,,, +Device,Logic Cells,Slices(1),Max Distributed RAM (Kb),DSP Slices(2),18 Kb,36 Kb,Max (Kb),CMTs(4),PCIe(5),GTXs,XADC,Total I/O Banks(6),Max User I/O(7) +XC7K70T,65600,10250,838,240,270,135,4860,6,1,8,1,6,300 +XC7K160T,162240,25350,2188,600,650,325,11700,8,1,8,1,8,400 +XC7K325T,326080,50950,4000,840,890,445,16020,10,1,16,1,10,500 +XC7K355T,356160,55650,5088,1440,1430,715,25740,6,1,24,1,6,300 +XC7K410T,406720,63550,5663,1540,1590,795,28620,10,1,16,1,10,500 +XC7K420T,416960,65150,5938,1680,1670,835,30060,8,1,32,1,8,400 +XC7K480T,477760,74650,6788,1920,1910,955,34380,8,1,32,1,8,400 +,,,,,,,,,,,,, +,,,,,,,,,,,,, +#,Notes: ,,,,,,,,,,,, +#,1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs. ,,,,,,,,,,,, +#,"2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator. ",,,,,,,,,,,, +#,3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks. ,,,,,,,,,,,, +#,4. Each CMT contains one MMCM and one PLL. ,,,,,,,,,,,, +#,5. Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2. ,,,,,,,,,,,, +#,6. Does not include configuration Bank 0. ,,,,,,,,,,,, +#,7. This number does not include GTX transceivers ,,,,,,,,,,,, diff --git a/Kintex-7/run.py b/Kintex-7/run.py new file mode 100755 index 0000000..c15aec5 --- /dev/null +++ b/Kintex-7/run.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python3 + +import csv +import os +import re +import shutil +import sys +from collections import defaultdict, namedtuple +from itertools import groupby +from jinja2 import Environment, FileSystemLoader, select_autoescape +from pathlib import Path + +env = Environment( + loader=FileSystemLoader("."), + trim_blocks=True, + lstrip_blocks=True, + autoescape=select_autoescape(['html', 'xml']) +) + +def index_by_header(rows): + item_keys = rows[0] + items = {k: {} for idx, k in enumerate(item_keys) if idx > 0} + fields = set() + for r_idx, row in enumerate(rows): + for c_idx, cell in enumerate(row): + if c_idx == 0: + field = cell + fields.add(field) + else: + key = item_keys[c_idx] + item = items[key] + item[field] = cell + return fields, items + +def table_to_map(table, keys_in: str = None): + if keys_in == "rows": + data = {} + fields = table[0] + for row in table[1:]: + key = row[0] + data[key] = o = {} + for idx, cell in enumerate(row): + field = fields[idx] + o[field] = cell + return data + else: + raise Exception("unknown keys_in value: {}".format(keys_in)) + +def read_csv(f, remove_notes = True): + table = [row for row in csv.reader(f) if not row[0].startswith("#") and len(row[0]) > 0] + if remove_notes: + r = r"\([0-9]+\)" + table[0] = [re.sub(r, "", name) for name in table[0]] + table[0] = [name.strip() for name in table[0]] + return table + +dbg = lambda x: '' +dbg = print +p = print + +Package = namedtuple("Package", "name size pitch") +PartPackage = namedtuple("PartPackage", "part package gtx hr hp") + +packages = {} +part_packages = {} + +with open("part-packages.csv") as f: + rows = read_csv(f) + +# for r in rows: +# print(r) + + package_indexes = [(idx, part) for idx, part in enumerate(rows[0]) if idx > 0 and len(part)] + + for idx, part in package_indexes: + name = rows[0][idx] + size = rows[1][idx] + pitch = rows[1][idx] + packages[name] = Package(name, size, pitch) + + print("Packages") + [print(" {}".format(p)) for p in packages] + + r = r"\([0-9]+\)" + + for row in rows[3:]: + part = row[0] + part_packages[part] = info = {} + + for idx, package in package_indexes: + gtx = row[idx] + hr = row[idx + 1] + hp = row[idx + 2] + if len(gtx) == 0: + continue + info[package] = PartPackage(part, package, gtx, hr, hp) + +print("Part/packages") +for part, packages in part_packages.items(): + print(" {}:".format(part)) + for pp in packages.values(): + print(" {}: gtx: {}, hr: {}, hp: {}".format(pp.package, pp.gtx, pp.hr, pp.hp)) + +if False: + sys.exit(1) + +with open("parts.csv") as f: + table = read_csv(f) + parts = table_to_map(table, keys_in="rows") + + out_dir = Path("mw") + if out_dir.exists(): + shutil.rmtree(out_dir) + out_dir.mkdir() + + print("parts") + for part, info in parts.items(): + print(info) + + for part in parts.values(): + part_number = part["Device"] + + print("--- PART: {} ---".format(part_number)) + path = out_dir / "Chip:{}.mw".format(part_number) + with open(path, "w") as out: + template = env.get_template("mw.j2") + out.write(template.render(part=part)) + for field in part: + print(field) |