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| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-29 18:30:06 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-29 18:30:06 +0000 |
| commit | 6d4cdddbe27d1b70528d9a70279a2a9b91c1f242 (patch) | |
| tree | 9a122cff72b64700a8002c6ab2cc14abc0969a76 /doc | |
| parent | 4297209ac91d62ab509284c142273ec38ec8cfe3 (diff) | |
| download | openocd+libswd-6d4cdddbe27d1b70528d9a70279a2a9b91c1f242.tar.gz openocd+libswd-6d4cdddbe27d1b70528d9a70279a2a9b91c1f242.tar.bz2 openocd+libswd-6d4cdddbe27d1b70528d9a70279a2a9b91c1f242.tar.xz openocd+libswd-6d4cdddbe27d1b70528d9a70279a2a9b91c1f242.zip | |
ARM11 command handling fixes
- Commands were supposed to have been "arm11 memwrite ..."
not "memwrite ..."
- Get rid of obfuscatory macros
- Re-alphabetize
- Add docs for "arm11 vcr"
git-svn-id: svn://svn.berlios.de/openocd/trunk@2776 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index d80ef492..28ec4a5d 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5496,10 +5496,23 @@ If @var{value} is defined, first assigns that. @deffn Command {arm11 step_irq_enable} [value] Displays the value of the flag controlling whether IRQs are enabled during single stepping; -they is disabled by default. +they are disabled by default. If @var{value} is defined, first assigns that. @end deffn +@deffn Command {arm11 vcr} [value] +@cindex vector_catch +Displays the value of the @emph{Vector Catch Register (VCR)}, +coprocessor 14 register 7. +If @var{value} is defined, first assigns that. + +Vector Catch hardware provides dedicated breakpoints +for certain hardware events. +The specific bit values are core-specific (as in fact is using +coprocessor 14 register 7 itself) but all current ARM11 +cores @emph{except the ARM1176} use the same six bits. +@end deffn + @section ARMv7 Architecture @cindex ARMv7 |