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authorØyvind Harboe <oyvind.harboe@zylin.com>2009-10-26 14:39:32 +0100
committerØyvind Harboe <oyvind.harboe@zylin.com>2009-11-10 13:13:13 +0100
commitc202ba7d34bd7feba88d7c0ee1aa9ef7be18bca9 (patch)
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parent1f357869c19cccdb3259eae10c1124af5c9510ff (diff)
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ARM11: remove old mrc/mcr commands
Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi20
1 files changed, 1 insertions, 19 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 86f5748f..8223ee94 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1502,7 +1502,7 @@ proc setc15 @{regs value@} @{
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
+ mcr 15 [expr ($regs>>12)&0x7] \
[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
[expr ($regs>>8)&0x7] $value
@}
@@ -5796,15 +5796,6 @@ Without arguments, the current settings are displayed.
@subsection ARM11 specific commands
@cindex ARM11
-@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
-Write @var{value} to a coprocessor @var{pX} register
-passing parameters @var{CRn},
-@var{CRm}, opcodes @var{opc1} and @var{opc2},
-and the MCR instruction.
-(The difference beween this and the MCR2 instruction is
-one bit in the encoding, effecively a fifth parameter.)
-@end deffn
-
@deffn Command {arm11 memwrite burst} [value]
Displays the value of the memwrite burst-enable flag,
which is enabled by default. Burst writes are only used
@@ -5821,15 +5812,6 @@ which is enabled by default.
If @var{value} is defined, first assigns that.
@end deffn
-@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
-Read a coprocessor @var{pX} register passing parameters @var{CRn},
-@var{CRm}, opcodes @var{opc1} and @var{opc2},
-and the MRC instruction.
-(The difference beween this and the MRC2 instruction is
-one bit in the encoding, effecively a fifth parameter.)
-Displays the result.
-@end deffn
-
@deffn Command {arm11 step_irq_enable} [value]
Displays the value of the flag controlling whether
IRQs are enabled during single stepping;