summaryrefslogtreecommitdiff
path: root/doc
diff options
context:
space:
mode:
authorDavid Brownell <dbrownell@users.sourceforge.net>2009-11-16 16:36:09 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-11-16 16:36:09 -0800
commitf86137066a6b42c46c457c9837a8015990bf71e6 (patch)
treeae2e1008558aecdcb52079ef2503bc5293e94968 /doc
parent7c393679c0cd8f7609a0d6b2329a1877de0f3d31 (diff)
downloadopenocd+libswd-f86137066a6b42c46c457c9837a8015990bf71e6.tar.gz
openocd+libswd-f86137066a6b42c46c457c9837a8015990bf71e6.tar.bz2
openocd+libswd-f86137066a6b42c46c457c9837a8015990bf71e6.tar.xz
openocd+libswd-f86137066a6b42c46c457c9837a8015990bf71e6.zip
ARM: "armv4_5" command prefix becomes "arm"
Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi14
1 files changed, 6 insertions, 8 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 81409acc..092de7d3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5515,16 +5515,14 @@ Reports whether the capture clock is locked or not.
@end deffn
-@section ARMv4 and ARMv5 Architecture
-@cindex ARMv4
-@cindex ARMv5
+@section Generic ARM
+@cindex ARM
-These commands are specific to ARM architecture v4 and v5,
-including all ARM7 or ARM9 systems and Intel XScale.
+These commands should be available on all ARM processors.
They are available in addition to other core-specific
commands that may be available.
-@deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
+@deffn Command {arm core_state} [@option{arm}|@option{thumb}]
Displays the core_state, optionally changing it to process
either @option{arm} or @option{thumb} instructions.
The target may later be resumed in the currently set core_state.
@@ -5532,7 +5530,7 @@ The target may later be resumed in the currently set core_state.
that is not currently supported in OpenOCD.)
@end deffn
-@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
+@deffn Command {arm disassemble} address [count [@option{thumb}]]
@cindex disassemble
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
@@ -5543,7 +5541,7 @@ else ARM (32-bit) instructions are used.
those instructions are not currently understood by OpenOCD.)
@end deffn
-@deffn Command {armv4_5 reg}
+@deffn Command {arm reg}
Display a table of all banked core registers, fetching the current value from every
core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
register value.